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ffa501ef19
Adding steering infrastructure for adding and removing optional counter. This allows to add and remove the counters dynamically in order not to hurt performance. Link: https://lore.kernel.org/r/20211008122439.166063-12-markzhang@nvidia.com Signed-off-by: Aharon Landau <aharonl@nvidia.com> Reviewed-by: Maor Gottlieb <maorg@nvidia.com> Signed-off-by: Leon Romanovsky <leonro@nvidia.com> Signed-off-by: Mark Zhang <markzhang@nvidia.com> Signed-off-by: Jason Gunthorpe <jgg@nvidia.com>
307 lines
6.8 KiB
C
307 lines
6.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0 OR BSD-3-Clause */
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/*
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* Copyright(c) 2016 - 2018 Intel Corporation.
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*/
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#ifndef IB_HDRS_H
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#define IB_HDRS_H
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#include <linux/types.h>
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#include <asm/unaligned.h>
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#include <rdma/ib_verbs.h>
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#define IB_SEQ_NAK (3 << 29)
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/* AETH NAK opcode values */
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#define IB_RNR_NAK 0x20
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#define IB_NAK_PSN_ERROR 0x60
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#define IB_NAK_INVALID_REQUEST 0x61
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#define IB_NAK_REMOTE_ACCESS_ERROR 0x62
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#define IB_NAK_REMOTE_OPERATIONAL_ERROR 0x63
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#define IB_NAK_INVALID_RD_REQUEST 0x64
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#define IB_BTH_REQ_ACK BIT(31)
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#define IB_BTH_SOLICITED BIT(23)
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#define IB_BTH_MIG_REQ BIT(22)
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#define IB_GRH_VERSION 6
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#define IB_GRH_VERSION_MASK 0xF
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#define IB_GRH_VERSION_SHIFT 28
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#define IB_GRH_TCLASS_MASK 0xFF
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#define IB_GRH_TCLASS_SHIFT 20
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#define IB_GRH_FLOW_MASK 0xFFFFF
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#define IB_GRH_FLOW_SHIFT 0
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#define IB_GRH_NEXT_HDR 0x1B
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#define IB_FECN_SHIFT 31
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#define IB_FECN_MASK 1
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#define IB_FECN_SMASK BIT(IB_FECN_SHIFT)
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#define IB_BECN_SHIFT 30
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#define IB_BECN_MASK 1
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#define IB_BECN_SMASK BIT(IB_BECN_SHIFT)
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#define IB_AETH_CREDIT_SHIFT 24
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#define IB_AETH_CREDIT_MASK 0x1F
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#define IB_AETH_CREDIT_INVAL 0x1F
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#define IB_AETH_NAK_SHIFT 29
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#define IB_MSN_MASK 0xFFFFFF
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struct ib_reth {
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__be64 vaddr; /* potentially unaligned */
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__be32 rkey;
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__be32 length;
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} __packed;
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struct ib_atomic_eth {
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__be64 vaddr; /* potentially unaligned */
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__be32 rkey;
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__be64 swap_data; /* potentially unaligned */
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__be64 compare_data; /* potentially unaligned */
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} __packed;
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#include <rdma/tid_rdma_defs.h>
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union ib_ehdrs {
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struct {
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__be32 deth[2];
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__be32 imm_data;
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} ud;
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struct {
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struct ib_reth reth;
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__be32 imm_data;
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} rc;
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struct {
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__be32 aeth;
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__be64 atomic_ack_eth; /* potentially unaligned */
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} __packed at;
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__be32 imm_data;
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__be32 aeth;
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__be32 ieth;
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struct ib_atomic_eth atomic_eth;
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/* TID RDMA headers */
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union {
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struct tid_rdma_read_req r_req;
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struct tid_rdma_read_resp r_rsp;
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struct tid_rdma_write_req w_req;
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struct tid_rdma_write_resp w_rsp;
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struct tid_rdma_write_data w_data;
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struct tid_rdma_resync resync;
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struct tid_rdma_ack ack;
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} tid_rdma;
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} __packed;
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struct ib_other_headers {
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__be32 bth[3];
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union ib_ehdrs u;
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} __packed;
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struct ib_header {
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__be16 lrh[4];
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union {
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struct {
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struct ib_grh grh;
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struct ib_other_headers oth;
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} l;
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struct ib_other_headers oth;
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} u;
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} __packed;
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/* accessors for unaligned __be64 items */
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static inline u64 ib_u64_get(__be64 *p)
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{
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return get_unaligned_be64(p);
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}
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static inline void ib_u64_put(u64 val, __be64 *p)
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{
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put_unaligned_be64(val, p);
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}
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static inline u64 get_ib_reth_vaddr(struct ib_reth *reth)
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{
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return ib_u64_get(&reth->vaddr);
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}
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static inline void put_ib_reth_vaddr(u64 val, struct ib_reth *reth)
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{
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ib_u64_put(val, &reth->vaddr);
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}
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static inline u64 get_ib_ateth_vaddr(struct ib_atomic_eth *ateth)
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{
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return ib_u64_get(&ateth->vaddr);
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}
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static inline void put_ib_ateth_vaddr(u64 val, struct ib_atomic_eth *ateth)
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{
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ib_u64_put(val, &ateth->vaddr);
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}
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static inline u64 get_ib_ateth_swap(struct ib_atomic_eth *ateth)
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{
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return ib_u64_get(&ateth->swap_data);
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}
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static inline void put_ib_ateth_swap(u64 val, struct ib_atomic_eth *ateth)
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{
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ib_u64_put(val, &ateth->swap_data);
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}
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static inline u64 get_ib_ateth_compare(struct ib_atomic_eth *ateth)
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{
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return ib_u64_get(&ateth->compare_data);
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}
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static inline void put_ib_ateth_compare(u64 val, struct ib_atomic_eth *ateth)
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{
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ib_u64_put(val, &ateth->compare_data);
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}
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/*
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* 9B/IB Packet Format
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*/
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#define IB_LNH_MASK 3
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#define IB_SC_MASK 0xf
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#define IB_SC_SHIFT 12
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#define IB_SC5_MASK 0x10
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#define IB_SL_MASK 0xf
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#define IB_SL_SHIFT 4
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#define IB_SL_SHIFT 4
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#define IB_LVER_MASK 0xf
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#define IB_LVER_SHIFT 8
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static inline u8 ib_get_lnh(struct ib_header *hdr)
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{
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return (be16_to_cpu(hdr->lrh[0]) & IB_LNH_MASK);
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}
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static inline u8 ib_get_sc(struct ib_header *hdr)
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{
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return ((be16_to_cpu(hdr->lrh[0]) >> IB_SC_SHIFT) & IB_SC_MASK);
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}
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static inline bool ib_is_sc5(u16 sc5)
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{
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return !!(sc5 & IB_SC5_MASK);
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}
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static inline u8 ib_get_sl(struct ib_header *hdr)
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{
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return ((be16_to_cpu(hdr->lrh[0]) >> IB_SL_SHIFT) & IB_SL_MASK);
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}
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static inline u16 ib_get_dlid(struct ib_header *hdr)
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{
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return (be16_to_cpu(hdr->lrh[1]));
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}
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static inline u16 ib_get_slid(struct ib_header *hdr)
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{
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return (be16_to_cpu(hdr->lrh[3]));
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}
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static inline u8 ib_get_lver(struct ib_header *hdr)
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{
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return (u8)((be16_to_cpu(hdr->lrh[0]) >> IB_LVER_SHIFT) &
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IB_LVER_MASK);
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}
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static inline u32 ib_get_qkey(struct ib_other_headers *ohdr)
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{
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return be32_to_cpu(ohdr->u.ud.deth[0]);
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}
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static inline u32 ib_get_sqpn(struct ib_other_headers *ohdr)
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{
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return ((be32_to_cpu(ohdr->u.ud.deth[1])) & IB_QPN_MASK);
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}
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/*
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* BTH
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*/
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#define IB_BTH_OPCODE_MASK 0xff
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#define IB_BTH_OPCODE_SHIFT 24
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#define IB_BTH_PAD_MASK 3
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#define IB_BTH_PKEY_MASK 0xffff
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#define IB_BTH_PAD_SHIFT 20
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#define IB_BTH_A_MASK 1
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#define IB_BTH_A_SHIFT 31
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#define IB_BTH_M_MASK 1
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#define IB_BTH_M_SHIFT 22
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#define IB_BTH_SE_MASK 1
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#define IB_BTH_SE_SHIFT 23
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#define IB_BTH_TVER_MASK 0xf
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#define IB_BTH_TVER_SHIFT 16
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#define IB_BTH_OPCODE_CNP 0x81
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static inline u8 ib_bth_get_pad(struct ib_other_headers *ohdr)
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{
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return ((be32_to_cpu(ohdr->bth[0]) >> IB_BTH_PAD_SHIFT) &
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IB_BTH_PAD_MASK);
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}
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static inline u16 ib_bth_get_pkey(struct ib_other_headers *ohdr)
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{
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return (be32_to_cpu(ohdr->bth[0]) & IB_BTH_PKEY_MASK);
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}
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static inline u8 ib_bth_get_opcode(struct ib_other_headers *ohdr)
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{
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return ((be32_to_cpu(ohdr->bth[0]) >> IB_BTH_OPCODE_SHIFT) &
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IB_BTH_OPCODE_MASK);
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}
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static inline u8 ib_bth_get_ackreq(struct ib_other_headers *ohdr)
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{
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return (u8)((be32_to_cpu(ohdr->bth[2]) >> IB_BTH_A_SHIFT) &
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IB_BTH_A_MASK);
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}
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static inline u8 ib_bth_get_migreq(struct ib_other_headers *ohdr)
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{
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return (u8)((be32_to_cpu(ohdr->bth[0]) >> IB_BTH_M_SHIFT) &
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IB_BTH_M_MASK);
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}
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static inline u8 ib_bth_get_se(struct ib_other_headers *ohdr)
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{
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return (u8)((be32_to_cpu(ohdr->bth[0]) >> IB_BTH_SE_SHIFT) &
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IB_BTH_SE_MASK);
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}
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static inline u32 ib_bth_get_psn(struct ib_other_headers *ohdr)
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{
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return (u32)(be32_to_cpu(ohdr->bth[2]));
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}
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static inline u32 ib_bth_get_qpn(struct ib_other_headers *ohdr)
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{
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return (u32)((be32_to_cpu(ohdr->bth[1])) & IB_QPN_MASK);
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}
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static inline bool ib_bth_get_becn(struct ib_other_headers *ohdr)
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{
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return (ohdr->bth[1]) & cpu_to_be32(IB_BECN_SMASK);
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}
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static inline bool ib_bth_get_fecn(struct ib_other_headers *ohdr)
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{
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return (ohdr->bth[1]) & cpu_to_be32(IB_FECN_SMASK);
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}
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static inline u8 ib_bth_get_tver(struct ib_other_headers *ohdr)
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{
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return (u8)((be32_to_cpu(ohdr->bth[0]) >> IB_BTH_TVER_SHIFT) &
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IB_BTH_TVER_MASK);
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}
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static inline bool ib_bth_is_solicited(struct ib_other_headers *ohdr)
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{
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return ohdr->bth[0] & cpu_to_be32(IB_BTH_SOLICITED);
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}
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static inline bool ib_bth_is_migration(struct ib_other_headers *ohdr)
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{
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return ohdr->bth[0] & cpu_to_be32(IB_BTH_MIG_REQ);
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}
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#endif /* IB_HDRS_H */
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