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947771d00b
Variscite has updated the Ethernet PHY on the VAR-SOM-MX93 from the ADIN1300BCPZ to the MaxLinear MXL86110, as documented in the August 2023 revision changelog. Link: https://variwiki.com/index.php?title=VAR-SOM-MX93_rev_changelog Update the device tree accordingly: - Drop the regulator node used to power the previously PHY. - Add support for the reset line using GPIO1_IO07 with proper timings. - Configure the PHY LEDs via the LED subsystem under /sys/class/leds/, leveraging the support implemented in the mxl86110 PHY driver (drivers/net/phy/mxl-86110.c). Two LEDs are defined to match the LED configuration on the Variscite VAR-SOM Carrier Boards: * LED@0: Yellow, netdev trigger. * LED@1: Green, netdev trigger. - Adjust the RGMII clock pad control settings to match the updated PHY requirements. These changes ensure proper PHY initialization and LED status indication for the new MaxLinear MXL86110, improving board compatibility with the latest hardware revision. Signed-off-by: Stefano Radaelli <stefano.radaelli21@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
126 lines
3.2 KiB
Text
126 lines
3.2 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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/*
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* Copyright 2022 NXP
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* Copyright 2023 Variscite Ltd.
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*/
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/dts-v1/;
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#include "imx93.dtsi"
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/{
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model = "Variscite VAR-SOM-MX93 module";
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compatible = "variscite,var-som-mx93", "fsl,imx93";
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mmc_pwrseq: mmc-pwrseq {
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compatible = "mmc-pwrseq-simple";
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post-power-on-delay-ms = <100>;
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power-off-delay-us = <10000>;
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reset-gpios = <&gpio4 14 GPIO_ACTIVE_LOW>, /* WIFI_RESET */
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<&gpio3 7 GPIO_ACTIVE_LOW>; /* WIFI_PWR_EN */
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};
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};
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&eqos {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_eqos>;
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/*
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* The required RGMII TX and RX 2ns delays are implemented directly
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* in hardware via passive delay elements on the SOM PCB.
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* No delay configuration is needed in software via PHY driver.
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*/
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phy-mode = "rgmii";
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phy-handle = <ðphy0>;
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snps,clk-csr = <5>;
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status = "okay";
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mdio {
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compatible = "snps,dwmac-mdio";
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#address-cells = <1>;
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#size-cells = <0>;
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clock-frequency = <1000000>;
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ethphy0: ethernet-phy@0 {
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compatible = "ethernet-phy-ieee802.3-c22";
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reg = <0>;
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eee-broken-1000t;
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reset-gpios = <&gpio1 7 GPIO_ACTIVE_LOW>;
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reset-assert-us = <10000>;
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reset-deassert-us = <100000>;
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leds {
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#address-cells = <1>;
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#size-cells = <0>;
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led@0 {
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reg = <0>;
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color = <LED_COLOR_ID_YELLOW>;
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function = LED_FUNCTION_LAN;
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linux,default-trigger = "netdev";
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};
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led@1 {
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reg = <1>;
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color = <LED_COLOR_ID_GREEN>;
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function = LED_FUNCTION_LAN;
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linux,default-trigger = "netdev";
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};
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};
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};
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};
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};
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/* eMMC */
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&usdhc1 {
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pinctrl-names = "default", "state_100mhz", "state_200mhz";
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pinctrl-0 = <&pinctrl_usdhc1>;
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pinctrl-1 = <&pinctrl_usdhc1>;
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pinctrl-2 = <&pinctrl_usdhc1>;
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bus-width = <8>;
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non-removable;
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status = "okay";
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};
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&iomuxc {
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pinctrl_eqos: eqosgrp {
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fsl,pins = <
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MX93_PAD_ENET1_MDC__ENET_QOS_MDC 0x57e
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MX93_PAD_ENET1_MDIO__ENET_QOS_MDIO 0x57e
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MX93_PAD_ENET1_RD0__ENET_QOS_RGMII_RD0 0x57e
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MX93_PAD_ENET1_RD1__ENET_QOS_RGMII_RD1 0x57e
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MX93_PAD_ENET1_RD2__ENET_QOS_RGMII_RD2 0x57e
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MX93_PAD_ENET1_RD3__ENET_QOS_RGMII_RD3 0x57e
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MX93_PAD_ENET1_RXC__CCM_ENET_QOS_CLOCK_GENERATE_RX_CLK 0x58e
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MX93_PAD_ENET1_RX_CTL__ENET_QOS_RGMII_RX_CTL 0x57e
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MX93_PAD_ENET1_TD0__ENET_QOS_RGMII_TD0 0x57e
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MX93_PAD_ENET1_TD1__ENET_QOS_RGMII_TD1 0x57e
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MX93_PAD_ENET1_TD2__ENET_QOS_RGMII_TD2 0x57e
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MX93_PAD_ENET1_TD3__ENET_QOS_RGMII_TD3 0x57e
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MX93_PAD_ENET1_TXC__CCM_ENET_QOS_CLOCK_GENERATE_TX_CLK 0x58e
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MX93_PAD_ENET1_TX_CTL__ENET_QOS_RGMII_TX_CTL 0x57e
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MX93_PAD_UART2_TXD__GPIO1_IO07 0x51e
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>;
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};
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pinctrl_reg_eqos_phy: regeqosgrp {
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fsl,pins = <
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MX93_PAD_UART2_TXD__GPIO1_IO07 0x51e
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>;
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};
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pinctrl_usdhc1: usdhc1grp {
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fsl,pins = <
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MX93_PAD_SD1_CLK__USDHC1_CLK 0x15fe
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MX93_PAD_SD1_CMD__USDHC1_CMD 0x13fe
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MX93_PAD_SD1_DATA0__USDHC1_DATA0 0x13fe
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MX93_PAD_SD1_DATA1__USDHC1_DATA1 0x13fe
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MX93_PAD_SD1_DATA2__USDHC1_DATA2 0x13fe
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MX93_PAD_SD1_DATA3__USDHC1_DATA3 0x13fe
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MX93_PAD_SD1_DATA4__USDHC1_DATA4 0x13fe
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MX93_PAD_SD1_DATA5__USDHC1_DATA5 0x13fe
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MX93_PAD_SD1_DATA6__USDHC1_DATA6 0x13fe
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MX93_PAD_SD1_DATA7__USDHC1_DATA7 0x13fe
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MX93_PAD_SD1_STROBE__USDHC1_STROBE 0x15fe
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>;
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};
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};
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