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linux/drivers/gpu
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Ville Syrjälä 2e523e98bb drm/i915: Implement chv display PHY lane stagger setup 
Set up the chv display PHY lane stagger registers according to
"Programming Guide for 1273 CHV eDP/DP/HDMI Display PHY" v1.04

Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com>
Reviewed-by:  Deepak S <deepak.s@linux.intel.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
2015-05-08 15:55:22 +02:00
..
drm drm/i915: Implement chv display PHY lane stagger setup 2015-05-08 15:55:22 +02:00
host1x gpu: host1x: Export host1x_syncpt_read() 2015-04-02 18:46:20 +02:00
ipu-v3 imx-drm changes to use media bus formats and LDB drm_panel support 2015-04-13 17:28:57 +10:00
vga
Makefile