Hawking Zhang 2d2fbf685c drm/amdgpu: use cached ih rb control reg offsets for navi10 ... all the ih rb control register offsets are cached at the beginning of navi10 ih_sw_init. Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com> Acked-by: Christian König <christian.koenig@amd.com> Acked-by: Felix Kuehling <Felix.Kuehling@amd.com> Reviewed-by: Dennis Li <Dennis.Li@amd.com> Reviewed-by: Feifei Xu <Feifei.Xu@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2020-12-23 15:05:02 -05:00
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acp
amdgpu	drm/amdgpu: use cached ih rb control reg offsets for navi10	2020-12-23 15:05:02 -05:00
amdkfd	drm/amdkfd: PCIe atomics required for gfx10	2020-12-17 16:43:14 -05:00
display	drm/amd/display: Fix memory leaks in S3 resume	2020-12-23 15:03:15 -05:00
include	drm/amdgpu: new macro for determining 2ND_USB20PORT support	2020-12-10 16:41:49 -05:00
pm	drm/amd/pm: bump Sienna Cichlid smu_driver_if version to match latest pmfw	2020-12-23 15:03:01 -05:00