Christophe Leroy 2c74e2586b powerpc/40x: Rework 40x PTE access and TLB miss ... Commit 1bc54c0311 ("powerpc: rework 4xx PTE access and TLB miss") reworked 44x PTE access to avoid atomic pte updates, and left 8xx, 40x and fsl booke with atomic pte updates. Commit 6cfd8990e2 ("powerpc: rework FSL Book-E PTE access and TLB miss") removed atomic pte updates on fsl booke. It went away on 8xx with commit ddfc20a3b9 ("powerpc/8xx: Remove PTE_ATOMIC_UPDATES"). 40x is the last platform setting PTE_ATOMIC_UPDATES. Rework PTE access and TLB miss to remove PTE_ATOMIC_UPDATES for 40x: - Always handle DSI as a fault. - Bail out of TLB miss handler when CONFIG_SWAP is set and _PAGE_ACCESSED is not set. - Bail out of ITLB miss handler when _PAGE_EXEC is not set. - Only set WR bit when both _PAGE_RW and _PAGE_DIRTY are set. - Remove _PAGE_HWWRITE - Don't require PTE_ATOMIC_UPDATES anymore Reported-by: kbuild test robot <lkp@intel.com> Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/99a0fcd337ef67088140d1647d75fea026a70413.1590079968.git.christophe.leroy@csgroup.eu		2020-05-28 23:24:34 +10:00
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32	powerpc/40x: Rework 40x PTE access and TLB miss	2020-05-28 23:24:34 +10:00
64	powerpc/mm: PTE_ATOMIC_UPDATES is only for 40x	2020-05-26 22:22:20 +10:00
hugetlb-book3e.h	powerpc/mm: cleanup ifdef mess in add_huge_page_size()	2019-05-03 01:20:23 +10:00
mmu-book3e.h	powerpc/fsl_booke/32: implement KASLR infrastructure	2019-11-13 19:27:40 +11:00
mmu.h	powerpc/mm: get rid of nohash/32/mmu.h and nohash/64/mmu.h	2019-05-03 01:20:24 +10:00
pgalloc.h	powerpc/mmu_gather: enable RCU_TABLE_FREE even for !SMP case	2020-02-04 03:05:25 +00:00
pgtable.h	powerpc/40x: Rework 40x PTE access and TLB miss	2020-05-28 23:24:34 +10:00
pte-book3e.h	powerpc/64: only book3s/64 supports CONFIG_PPC_64K_PAGES	2019-05-03 01:20:23 +10:00
tlbflush.h	powerpc: split asm/tlbflush.h	2018-07-30 22:48:21 +10:00