Xiaojie Yuan 87190edcf3 drm/amdgpu: add CGTT_GS_NGG_CLK_CTRL register to gc header ... gc 10.1.2 introduced this new register Signed-off-by: Xiaojie Yuan <xiaojie.yuan@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2019-08-02 10:30:40 -05:00
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asic_reg	drm/amdgpu: add CGTT_GS_NGG_CLK_CTRL register to gc header	2019-08-02 10:30:40 -05:00
ivsrcid
amd_acpi.h
amd_pcie.h
amd_pcie_helpers.h
amd_shared.h
arct_ip_offset.h	drm/amd/include: adjust base offset of SMUIO and THM for Arcturus	2019-07-30 23:48:34 -05:00
atom-bits.h
atom-names.h
atom-types.h
atombios.h
atomfirmware.h
atomfirmwareid.h
cgs_common.h
cik_structs.h
discovery.h
displayobject.h
dm_pp_interface.h
kgd_kfd_interface.h
kgd_pp_interface.h	drm/amd/powerplay: add new sensor type for VCN powergate status	2019-07-30 23:48:34 -05:00
navi10_enum.h
navi10_ip_offset.h
navi12_ip_offset.h	drm/amdgpu: add ip offset header for navi12 (v2)	2019-08-02 10:30:39 -05:00
navi14_ip_offset.h
pptable.h
soc15_hw_ip.h
soc15_ih_clientid.h
v9_structs.h	drm/amdkfd: Extend CU mask to 8 SEs (v3)	2019-08-02 10:19:11 -05:00
v10_structs.h
vega10_enum.h
vega10_ip_offset.h
vega20_ip_offset.h
vi_structs.h