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SDM845 SoC includes the Mobile Display Sub System (MDSS) which is a top level wrapper consisting of Display Processing Unit (DPU) and display peripheral modules such as Display Serial Interface (DSI) and DisplayPort (DP). MDSS functions essentially as a back-end composition engine. It blends video and graphic images stored in the frame buffers and scans out the composed image to a display sink (over DSI/DP). The following diagram represents hardware blocks for a simple pipeline (two planes are present on a given crtc which is connected to a DSI connector): MDSS +---------------------------------+ | +-----------------------------+ | | | DPU | | | | +--------+ +--------+ | | | | | SSPP | | SSPP | | | | | +----+---+ +----+---+ | | | | | | | | | | +----v-----------v---+ | | | | | Layer Mixer (LM) | | | | | +--------------------+ | | | | +--------------------+ | | | | | PingPong (PP) | | | | | +--------------------+ | | | | +--------------------+ | | | | | INTERFACE (VIDEO) | | | | | +---+----------------+ | | | +------|----------------------+ | | | | | +------|---------------------+ | | | | DISPLAY PERIPHERALS | | | | +---v-+ +-----+ | | | | | DSI | | DP | | | | | +-----+ +-----+ | | | +----------------------------+ | +---------------------------------+ The number of DPU sub-blocks (i.e. SSPPs, LMs, PP blocks and INTFs) depends on SoC capabilities. Overview of DPU sub-blocks: --------------------------- * Source Surface Processor (SSPP): Refers to any of hardware pipes like ViG, DMA etc. Only ViG pipes are capable of performing format conversion, scaling and quality improvement for source surfaces. * Layer Mixer (LM): Blend source surfaces together (in requested zorder) * PingPong (PP): This block controls frame done interrupt output, EOL and EOF generation, overflow/underflow control. * Display interface (INTF): Timing generator and interface connecting the display peripherals. DRM components mapping to DPU architecture: ------------------------------------------ PLANEs maps to SSPPs CRTC maps to LMs Encoder maps to PPs, INTFs Data flow setup: --------------- MDSS hardware can support various data flows (e.g.): - Dual pipe: Output from two LMs combined to single display. - Split display: Output from two LMs connected to two separate interfaces. The hardware capabilities determine the number of concurrent data paths possible. Any control path (i.e. pipeline w/i DPU) can be routed to any of the hardware data paths. A given control path can be triggered, flushed and controlled independently. Changes in v3: - Move msm_media_info.h from uapi to dpu/ subdir - Remove preclose callback dpu (it's handled in core) - Fix kbuild warnings with parent_ops - Remove unused functions from dpu_core_irq - Rename mdss_phys to mdss - Rename mdp_phys address space to mdp - Drop _phys from vbif and regdma binding names Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org> Signed-off-by: Archit Taneja <architt@codeaurora.org> Signed-off-by: Chandan Uddaraju <chandanu@codeaurora.org> Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org> Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> Signed-off-by: Rajesh Yadav <ryadav@codeaurora.org> Signed-off-by: Sravanthi Kollukuduru <skolluku@codeaurora.org> Signed-off-by: Sean Paul <seanpaul@chromium.org> [robclark minor rebase] Signed-off-by: Rob Clark <robdclark@gmail.com>
191 lines
6.8 KiB
C
191 lines
6.8 KiB
C
/*
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* Copyright (c) 2015-2018, The Linux Foundation. All rights reserved.
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* Copyright (C) 2013 Red Hat
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* Author: Rob Clark <robdclark@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#ifndef __DPU_ENCODER_H__
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#define __DPU_ENCODER_H__
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#include <drm/drm_crtc.h>
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#include "dpu_hw_mdss.h"
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#define DPU_ENCODER_FRAME_EVENT_DONE BIT(0)
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#define DPU_ENCODER_FRAME_EVENT_ERROR BIT(1)
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#define DPU_ENCODER_FRAME_EVENT_PANEL_DEAD BIT(2)
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#define DPU_ENCODER_FRAME_EVENT_IDLE BIT(3)
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#define IDLE_TIMEOUT (66 - 16/2)
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/**
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* Encoder functions and data types
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* @intfs: Interfaces this encoder is using, INTF_MODE_NONE if unused
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* @needs_cdm: Encoder requests a CDM based on pixel format conversion needs
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* @display_num_of_h_tiles: Number of horizontal tiles in case of split
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* interface
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* @topology: Topology of the display
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*/
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struct dpu_encoder_hw_resources {
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enum dpu_intf_mode intfs[INTF_MAX];
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bool needs_cdm;
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u32 display_num_of_h_tiles;
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};
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/**
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* dpu_encoder_kickoff_params - info encoder requires at kickoff
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* @affected_displays: bitmask, bit set means the ROI of the commit lies within
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* the bounds of the physical display at the bit index
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*/
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struct dpu_encoder_kickoff_params {
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unsigned long affected_displays;
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};
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/**
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* dpu_encoder_get_hw_resources - Populate table of required hardware resources
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* @encoder: encoder pointer
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* @hw_res: resource table to populate with encoder required resources
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* @conn_state: report hw reqs based on this proposed connector state
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*/
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void dpu_encoder_get_hw_resources(struct drm_encoder *encoder,
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struct dpu_encoder_hw_resources *hw_res,
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struct drm_connector_state *conn_state);
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/**
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* dpu_encoder_register_vblank_callback - provide callback to encoder that
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* will be called on the next vblank.
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* @encoder: encoder pointer
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* @cb: callback pointer, provide NULL to deregister and disable IRQs
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* @data: user data provided to callback
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*/
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void dpu_encoder_register_vblank_callback(struct drm_encoder *encoder,
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void (*cb)(void *), void *data);
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/**
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* dpu_encoder_register_frame_event_callback - provide callback to encoder that
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* will be called after the request is complete, or other events.
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* @encoder: encoder pointer
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* @cb: callback pointer, provide NULL to deregister
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* @data: user data provided to callback
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*/
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void dpu_encoder_register_frame_event_callback(struct drm_encoder *encoder,
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void (*cb)(void *, u32), void *data);
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/**
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* dpu_encoder_prepare_for_kickoff - schedule double buffer flip of the ctl
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* path (i.e. ctl flush and start) at next appropriate time.
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* Immediately: if no previous commit is outstanding.
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* Delayed: Block until next trigger can be issued.
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* @encoder: encoder pointer
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* @params: kickoff time parameters
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*/
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void dpu_encoder_prepare_for_kickoff(struct drm_encoder *encoder,
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struct dpu_encoder_kickoff_params *params);
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/**
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* dpu_encoder_trigger_kickoff_pending - Clear the flush bits from previous
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* kickoff and trigger the ctl prepare progress for command mode display.
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* @encoder: encoder pointer
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*/
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void dpu_encoder_trigger_kickoff_pending(struct drm_encoder *encoder);
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/**
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* dpu_encoder_kickoff - trigger a double buffer flip of the ctl path
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* (i.e. ctl flush and start) immediately.
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* @encoder: encoder pointer
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*/
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void dpu_encoder_kickoff(struct drm_encoder *encoder);
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/**
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* dpu_encoder_wait_for_event - Waits for encoder events
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* @encoder: encoder pointer
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* @event: event to wait for
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* MSM_ENC_COMMIT_DONE - Wait for hardware to have flushed the current pending
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* frames to hardware at a vblank or ctl_start
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* Encoders will map this differently depending on the
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* panel type.
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* vid mode -> vsync_irq
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* cmd mode -> ctl_start
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* MSM_ENC_TX_COMPLETE - Wait for the hardware to transfer all the pixels to
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* the panel. Encoders will map this differently
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* depending on the panel type.
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* vid mode -> vsync_irq
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* cmd mode -> pp_done
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* Returns: 0 on success, -EWOULDBLOCK if already signaled, error otherwise
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*/
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int dpu_encoder_wait_for_event(struct drm_encoder *drm_encoder,
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enum msm_event_wait event);
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/*
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* dpu_encoder_get_intf_mode - get interface mode of the given encoder
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* @encoder: Pointer to drm encoder object
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*/
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enum dpu_intf_mode dpu_encoder_get_intf_mode(struct drm_encoder *encoder);
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/**
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* dpu_encoder_virt_restore - restore the encoder configs
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* @encoder: encoder pointer
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*/
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void dpu_encoder_virt_restore(struct drm_encoder *encoder);
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/**
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* dpu_encoder_check_mode - check if given mode is supported or not
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* @drm_enc: Pointer to drm encoder object
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* @mode: Mode to be checked
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* @Return: true if it is cmd mode
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*/
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bool dpu_encoder_check_mode(struct drm_encoder *drm_enc, u32 mode);
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/**
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* dpu_encoder_init - initialize virtual encoder object
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* @dev: Pointer to drm device structure
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* @disp_info: Pointer to display information structure
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* Returns: Pointer to newly created drm encoder
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*/
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struct drm_encoder *dpu_encoder_init(
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struct drm_device *dev,
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int drm_enc_mode);
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/**
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* dpu_encoder_setup - setup dpu_encoder for the display probed
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* @dev: Pointer to drm device structure
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* @enc: Pointer to the drm_encoder
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* @disp_info: Pointer to the display info
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*/
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int dpu_encoder_setup(struct drm_device *dev, struct drm_encoder *enc,
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struct msm_display_info *disp_info);
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/**
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* dpu_encoder_destroy - destroy previously initialized virtual encoder
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* @drm_enc: Pointer to previously created drm encoder structure
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*/
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void dpu_encoder_destroy(struct drm_encoder *drm_enc);
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/**
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* dpu_encoder_prepare_commit - prepare encoder at the very beginning of an
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* atomic commit, before any registers are written
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* @drm_enc: Pointer to previously created drm encoder structure
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*/
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void dpu_encoder_prepare_commit(struct drm_encoder *drm_enc);
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/**
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* dpu_encoder_set_idle_timeout - set the idle timeout for video
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* and command mode encoders.
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* @drm_enc: Pointer to previously created drm encoder structure
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* @idle_timeout: idle timeout duration in milliseconds
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*/
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void dpu_encoder_set_idle_timeout(struct drm_encoder *drm_enc,
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u32 idle_timeout);
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#endif /* __DPU_ENCODER_H__ */
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