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2264d9c74d
We use the cpu hotplug notifier to catch each cpu in turn and look at its cache topology w.r.t each of the resource groups. As we discover new resources, we initialize the bitmask array for each to the default (full access) value. Signed-off-by: Tony Luck <tony.luck@intel.com> Signed-off-by: Fenghua Yu <fenghua.yu@intel.com> Cc: "Ravi V Shankar" <ravi.v.shankar@intel.com> Cc: "Shaohua Li" <shli@fb.com> Cc: "Sai Prakhya" <sai.praneeth.prakhya@intel.com> Cc: "Peter Zijlstra" <peterz@infradead.org> Cc: "Stephane Eranian" <eranian@google.com> Cc: "Dave Hansen" <dave.hansen@intel.com> Cc: "David Carrillo-Cisneros" <davidcc@google.com> Cc: "Nilay Vaish" <nilayvaish@gmail.com> Cc: "Vikas Shivappa" <vikas.shivappa@linux.intel.com> Cc: "Ingo Molnar" <mingo@elte.hu> Cc: "Borislav Petkov" <bp@suse.de> Cc: "H. Peter Anvin" <h.peter.anvin@intel.com> Link: http://lkml.kernel.org/r/1477692289-37412-3-git-send-email-fenghua.yu@intel.com Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
109 lines
2.6 KiB
C
109 lines
2.6 KiB
C
#ifndef _ASM_X86_INTEL_RDT_H
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#define _ASM_X86_INTEL_RDT_H
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#define IA32_L3_CBM_BASE 0xc90
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#define IA32_L2_CBM_BASE 0xd10
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/**
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* struct rdt_resource - attributes of an RDT resource
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* @enabled: Is this feature enabled on this machine
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* @capable: Is this feature available on this machine
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* @name: Name to use in "schemata" file
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* @num_closid: Number of CLOSIDs available
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* @max_cbm: Largest Cache Bit Mask allowed
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* @min_cbm_bits: Minimum number of consecutive bits to be set
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* in a cache bit mask
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* @domains: All domains for this resource
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* @num_domains: Number of domains active
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* @msr_base: Base MSR address for CBMs
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* @tmp_cbms: Scratch space when updating schemata
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* @cache_level: Which cache level defines scope of this domain
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* @cbm_idx_multi: Multiplier of CBM index
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* @cbm_idx_offset: Offset of CBM index. CBM index is computed by:
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* closid * cbm_idx_multi + cbm_idx_offset
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*/
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struct rdt_resource {
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bool enabled;
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bool capable;
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char *name;
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int num_closid;
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int cbm_len;
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int min_cbm_bits;
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u32 max_cbm;
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struct list_head domains;
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int num_domains;
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int msr_base;
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u32 *tmp_cbms;
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int cache_level;
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int cbm_idx_multi;
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int cbm_idx_offset;
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};
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/**
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* struct rdt_domain - group of cpus sharing an RDT resource
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* @list: all instances of this resource
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* @id: unique id for this instance
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* @cpu_mask: which cpus share this resource
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* @cbm: array of cache bit masks (indexed by CLOSID)
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*/
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struct rdt_domain {
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struct list_head list;
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int id;
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struct cpumask cpu_mask;
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u32 *cbm;
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};
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/**
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* struct msr_param - set a range of MSRs from a domain
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* @res: The resource to use
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* @low: Beginning index from base MSR
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* @high: End index
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*/
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struct msr_param {
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struct rdt_resource *res;
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int low;
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int high;
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};
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extern struct mutex rdtgroup_mutex;
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extern struct rdt_resource rdt_resources_all[];
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enum {
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RDT_RESOURCE_L3,
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RDT_RESOURCE_L3DATA,
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RDT_RESOURCE_L3CODE,
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RDT_RESOURCE_L2,
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/* Must be the last */
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RDT_NUM_RESOURCES,
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};
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#define for_each_capable_rdt_resource(r) \
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for (r = rdt_resources_all; r < rdt_resources_all + RDT_NUM_RESOURCES;\
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r++) \
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if (r->capable)
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#define for_each_enabled_rdt_resource(r) \
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for (r = rdt_resources_all; r < rdt_resources_all + RDT_NUM_RESOURCES;\
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r++) \
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if (r->enabled)
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/* CPUID.(EAX=10H, ECX=ResID=1).EAX */
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union cpuid_0x10_1_eax {
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struct {
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unsigned int cbm_len:5;
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} split;
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unsigned int full;
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};
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/* CPUID.(EAX=10H, ECX=ResID=1).EDX */
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union cpuid_0x10_1_edx {
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struct {
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unsigned int cos_max:16;
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} split;
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unsigned int full;
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};
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void rdt_cbm_update(void *arg);
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#endif /* _ASM_X86_INTEL_RDT_H */
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