Huacai Chen 1e820da3c9 MIPS: Loongson-3: Introduce CONFIG_LOONGSON3_ENHANCEMENT ... New Loongson 3 CPU (since Loongson-3A R2, as opposed to Loongson-3A R1, Loongson-3B R1 and Loongson-3B R2) has many enhancements, such as FTLB, L1-VCache, EI/DI/Wait/Prefetch instruction, DSP/DSPv2 ASE, User Local register, Read-Inhibit/Execute-Inhibit, SFB (Store Fill Buffer), Fast TLB refill support, etc. This patch introduce a config option, CONFIG_LOONGSON3_ENHANCEMENT, to enable those enhancements which are not probed at run time. If you want a generic kernel to run on all Loongson 3 machines, please say 'N' here. If you want a high-performance kernel to run on new Loongson 3 machines only, please say 'Y' here. Some additional explanations: 1) SFB locates between core and L1 cache, it causes memory access out of order, so writel/outl (and other similar functions) need a I/O reorder barrier. 2) Loongson 3 has a bug that di instruction can not save the irqflag, so arch_local_irq_save() is modified. Since CPU_MIPSR2 is selected by CONFIG_LOONGSON3_ENHANCEMENT, generic kernel doesn't use ei/di at all. 3) CPU_HAS_PREFETCH is selected by CONFIG_LOONGSON3_ENHANCEMENT, so MIPS_CPU_PREFETCH (used by uasm) probing is also put in this patch. Signed-off-by: Huacai Chen <chenhc@lemote.com> Cc: Aurelien Jarno <aurelien@aurel32.net> Cc: Steven J . Hill <sjhill@realitydiluted.com> Cc: Fuxin Zhang <zhangfx@lemote.com> Cc: Zhangjin Wu <wuzhangjin@gmail.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/12755/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>		2016-05-13 14:02:15 +02:00
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c-octeon.c	MIPS: Call find_vma with the mmap_sem held	2014-06-03 22:19:09 +02:00
c-r3k.c
c-r4k.c	MIPS: Loongson-3: Introduce CONFIG_LOONGSON3_ENHANCEMENT	2016-05-13 14:02:15 +02:00
c-tx39.c	MIPS: tlb-r3k: Move CP0.Wired register initialisation to `tlb_init'	2015-06-21 21:52:41 +02:00
cache.c	MIPS: Sync icache & dcache in set_pte_at	2016-05-13 14:01:58 +02:00
cerr-sb1.c
cex-gen.S
cex-oct.S
cex-sb1.S
dma-default.c	MIPS: dma-default: Defend against NULL dev in massage_gfp_flags	2016-05-09 12:00:04 +02:00
extable.c
fault.c	MIPS: Set trap_no field in thread_struct on exception.	2015-09-03 12:08:04 +02:00
gup.c	Merge branch 'mm-pkeys-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip	2016-03-20 19:08:56 -07:00
highmem.c	kmap_atomic_to_page() has no users, remove it	2015-11-09 15:11:24 -08:00
hugetlbpage.c	mm/hugetlb: reduce arch dependent code about huge_pmd_unshare	2015-06-24 17:49:41 -07:00
init.c	MIPS: c-r4k: Sync icache when it fills from dcache	2016-05-09 12:00:02 +02:00
ioremap.c	MIPS: Replace use of phys_t with phys_addr_t.	2014-11-24 22:47:31 +01:00
Makefile	MIPS: Allow L2 prefetch to be configured via debugfs	2015-10-26 09:49:42 +01:00
mmap.c	mm: ASLR: use get_random_long()	2016-02-27 10:28:52 -08:00
page-funcs.S
page.c	MIPS: Loongson-3: Introduce CONFIG_LOONGSON3_ENHANCEMENT	2016-05-13 14:02:15 +02:00
pgtable-32.c
pgtable-64.c	mips, thp: remove infrastructure for handling splitting PMDs	2016-01-15 17:56:32 -08:00
sc-debugfs.c	MIPS: Allow L2 prefetch to be configured via debugfs	2015-10-26 09:49:42 +01:00
sc-ip22.c	MIPS: Fix misspellings in comments.	2016-04-03 12:32:09 +02:00
sc-mips.c	MIPS: Add P6600 cases to CPU switch statements	2016-05-13 14:01:52 +02:00
sc-r5k.c	MIPS: Remove useless parentheses	2014-11-24 07:44:49 +01:00
sc-rm7k.c
tlb-funcs.S	MIPS: mm: Fix broken microMIPS kernel regression.	2014-05-14 18:11:06 +02:00
tlb-r3k.c	MIPS: Refactor dumping of TLB registers for r3k/r4k	2015-09-03 12:07:45 +02:00
tlb-r4k.c	MIPS: Loongson: Invalidate special TLBs when needed	2016-05-13 14:02:14 +02:00
tlb-r8k.c
tlbex-fault.S
tlbex.c	MIPS: Loongson-3: Fast TLB refill handler	2016-05-13 14:02:15 +02:00
uasm-micromips.c	MIPS: mm: Remove dead macro definitions	2015-02-20 23:42:00 +01:00
uasm-mips.c	MIPS: Loongson-3: Fast TLB refill handler	2016-05-13 14:02:15 +02:00
uasm.c	MIPS: Loongson-3: Fast TLB refill handler	2016-05-13 14:02:15 +02:00