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1dfdc6501a
Current Renesas sound driver is assuming that all Sampling rate and channles are possible to use, but these are depends on inputed clock and SSI connection situation. For example, if it is using 1 SSI, enabled TDM mode and has 12288000 input clock, 2ch output can support until 192000Hz, but 6ch output can support until 64000Hz, 8ch can support 48000Hz. To control these situation correctly, it needs to support hw_constraints / refine feature. To support such feature, it needs SSI clock query feature, and it needs ADG clock query feature. Current ADG has rsnd_adg_ssi_clk_try_start() and it is doing similar things, but it try to setup ADG register in same time. This is not needed. This patch adds new rsnd_adg_clk_query() and separates query feature and register setting feature in adg.c Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com> Tested-by: Hiroyuki Yokoyama <hiroyuki.yokoyama.vx@renesas.com> Signed-off-by: Mark Brown <broonie@kernel.org> |
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| .. | ||
| rcar | ||
| dma-sh7760.c | ||
| fsi.c | ||
| hac.c | ||
| Kconfig | ||
| Makefile | ||
| migor.c | ||
| sh7760-ac97.c | ||
| siu.h | ||
| siu_dai.c | ||
| siu_pcm.c | ||
| ssi.c | ||