Dillon Varone 33151fb787 drm/amd/display: Set memclk levels to be at least 1 for dcn32 ... [Why] Cannot report 0 memclk levels even when SMU does not provide any. [How] When memclk levels reported by SMU is 0, set levels to 1. Tested-by: Mark Broadworth <mark.broadworth@amd.com> Reviewed-by: Martin Leung <Martin.Leung@amd.com> Acked-by: Rodrigo Siqueira <Rodrigo.Siqueira@amd.com> Signed-off-by: Dillon Varone <Dillon.Varone@amd.com> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>		2022-10-27 14:43:20 -04:00
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dce60
dce100	drm/amd/display: remove dtbclk_ss compensation for dcn316	2022-04-12 14:18:18 -04:00
dce110
dce112
dce120
dcn10
dcn20	drm/amd/display: increase hardware status wait time	2022-10-10 17:17:48 -04:00
dcn21	drm/amd/display: remove header from source file	2022-08-10 14:58:37 -04:00
dcn30	drm/amd/display: move FPU code from dcn30 clk mgr to DML folder	2022-07-25 09:31:05 -04:00
dcn31	drm/amd/display: Display distortion after hotplug 5K tiled display	2022-09-19 15:14:46 -04:00
dcn32	drm/amd/display: Set memclk levels to be at least 1 for dcn32	2022-10-27 14:43:20 -04:00
dcn201	drm/amd/display: Clean up some inconsistent indenting	2022-07-28 16:05:15 -04:00
dcn301	drm/amd/display: move FPU code from dcn301 clk mgr to DML folder	2022-07-25 09:31:05 -04:00
dcn314	drm/amd/display: Update PMFW z-state interface for DCN314	2022-10-10 17:11:41 -04:00
dcn315	drm/amd/display: correctly populate dcn315 clock table	2022-10-24 14:35:46 -04:00
dcn316	drm/amd/display: Display distortion after hotplug 5K tiled display	2022-09-19 15:14:46 -04:00
clk_mgr.c	drm/amd/display: change family id name for DCN314	2022-08-10 15:10:12 -04:00
Makefile	drm/amd/display: move FPU code from dcn301 clk mgr to DML folder	2022-07-25 09:31:05 -04:00