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![]() When TLB entries are invalidated in the presence of a virtually tagged icache, such as that found on Octeon CPUs, flush the icache so that we don't get a reserved instruction exception even though the TLB mapping is removed. Signed-off-by: James Hogan <james.hogan@imgtec.com> Cc: Paolo Bonzini <pbonzini@redhat.com> Cc: "Radim Krčmář" <rkrcmar@redhat.com> Cc: Ralf Baechle <ralf@linux-mips.org> Cc: David Daney <david.daney@cavium.com> Cc: Andreas Herrmann <andreas.herrmann@caviumnetworks.com> Cc: linux-mips@linux-mips.org Cc: kvm@vger.kernel.org |
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.. | ||
00README.txt | ||
callback.c | ||
commpage.c | ||
commpage.h | ||
dyntrans.c | ||
emulate.c | ||
entry.c | ||
fpu.S | ||
hypcall.c | ||
interrupt.c | ||
interrupt.h | ||
Kconfig | ||
Makefile | ||
mips.c | ||
mmu.c | ||
msa.S | ||
stats.c | ||
tlb.c | ||
trace.h | ||
trap_emul.c | ||
vz.c |