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357fb60502
With this, now all combinations of CBC: AES, 3DES-EDE with HMAC: SHA-1, SHA-224, SHA-256, SHA-384, SHA-512 are supported. Signed-off-by: Horia Geanta <horia.geanta@freescale.com> Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
351 lines
14 KiB
C
351 lines
14 KiB
C
/*
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* Freescale SEC (talitos) device register and descriptor header defines
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*
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* Copyright (c) 2006-2011 Freescale Semiconductor, Inc.
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the distribution.
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* 3. The name of the author may not be used to endorse or promote products
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* derived from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
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* IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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* OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
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* IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
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* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
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* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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*/
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#define TALITOS_TIMEOUT 100000
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#define TALITOS_MAX_DATA_LEN 65535
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#define DESC_TYPE(desc_hdr) ((be32_to_cpu(desc_hdr) >> 3) & 0x1f)
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#define PRIMARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 28) & 0xf)
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#define SECONDARY_EU(desc_hdr) ((be32_to_cpu(desc_hdr) >> 16) & 0xf)
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/* descriptor pointer entry */
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struct talitos_ptr {
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__be16 len; /* length */
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u8 j_extent; /* jump to sg link table and/or extent */
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u8 eptr; /* extended address */
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__be32 ptr; /* address */
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};
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static const struct talitos_ptr zero_entry = {
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.len = 0,
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.j_extent = 0,
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.eptr = 0,
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.ptr = 0
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};
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/* descriptor */
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struct talitos_desc {
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__be32 hdr; /* header high bits */
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__be32 hdr_lo; /* header low bits */
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struct talitos_ptr ptr[7]; /* ptr/len pair array */
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};
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/**
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* talitos_request - descriptor submission request
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* @desc: descriptor pointer (kernel virtual)
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* @dma_desc: descriptor's physical bus address
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* @callback: whom to call when descriptor processing is done
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* @context: caller context (optional)
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*/
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struct talitos_request {
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struct talitos_desc *desc;
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dma_addr_t dma_desc;
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void (*callback) (struct device *dev, struct talitos_desc *desc,
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void *context, int error);
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void *context;
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};
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/* per-channel fifo management */
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struct talitos_channel {
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void __iomem *reg;
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/* request fifo */
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struct talitos_request *fifo;
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/* number of requests pending in channel h/w fifo */
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atomic_t submit_count ____cacheline_aligned;
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/* request submission (head) lock */
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spinlock_t head_lock ____cacheline_aligned;
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/* index to next free descriptor request */
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int head;
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/* request release (tail) lock */
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spinlock_t tail_lock ____cacheline_aligned;
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/* index to next in-progress/done descriptor request */
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int tail;
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};
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struct talitos_private {
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struct device *dev;
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struct platform_device *ofdev;
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void __iomem *reg;
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int irq[2];
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/* SEC global registers lock */
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spinlock_t reg_lock ____cacheline_aligned;
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/* SEC version geometry (from device tree node) */
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unsigned int num_channels;
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unsigned int chfifo_len;
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unsigned int exec_units;
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unsigned int desc_types;
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/* SEC Compatibility info */
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unsigned long features;
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/*
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* length of the request fifo
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* fifo_len is chfifo_len rounded up to next power of 2
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* so we can use bitwise ops to wrap
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*/
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unsigned int fifo_len;
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struct talitos_channel *chan;
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/* next channel to be assigned next incoming descriptor */
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atomic_t last_chan ____cacheline_aligned;
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/* request callback tasklet */
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struct tasklet_struct done_task[2];
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/* list of registered algorithms */
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struct list_head alg_list;
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/* hwrng device */
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struct hwrng rng;
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};
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extern int talitos_submit(struct device *dev, int ch, struct talitos_desc *desc,
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void (*callback)(struct device *dev,
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struct talitos_desc *desc,
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void *context, int error),
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void *context);
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/* .features flag */
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#define TALITOS_FTR_SRC_LINK_TBL_LEN_INCLUDES_EXTENT 0x00000001
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#define TALITOS_FTR_HW_AUTH_CHECK 0x00000002
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#define TALITOS_FTR_SHA224_HWINIT 0x00000004
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#define TALITOS_FTR_HMAC_OK 0x00000008
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/*
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* TALITOS_xxx_LO addresses point to the low data bits (32-63) of the register
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*/
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/* global register offset addresses */
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#define TALITOS_MCR 0x1030 /* master control register */
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#define TALITOS_MCR_RCA0 (1 << 15) /* remap channel 0 */
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#define TALITOS_MCR_RCA1 (1 << 14) /* remap channel 1 */
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#define TALITOS_MCR_RCA2 (1 << 13) /* remap channel 2 */
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#define TALITOS_MCR_RCA3 (1 << 12) /* remap channel 3 */
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#define TALITOS_MCR_SWR 0x1 /* s/w reset */
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#define TALITOS_MCR_LO 0x1034
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#define TALITOS_IMR 0x1008 /* interrupt mask register */
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#define TALITOS_IMR_INIT 0x100ff /* enable channel IRQs */
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#define TALITOS_IMR_DONE 0x00055 /* done IRQs */
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#define TALITOS_IMR_LO 0x100C
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#define TALITOS_IMR_LO_INIT 0x20000 /* allow RNGU error IRQs */
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#define TALITOS_ISR 0x1010 /* interrupt status register */
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#define TALITOS_ISR_4CHERR 0xaa /* 4 channel errors mask */
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#define TALITOS_ISR_4CHDONE 0x55 /* 4 channel done mask */
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#define TALITOS_ISR_CH_0_2_ERR 0x22 /* channels 0, 2 errors mask */
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#define TALITOS_ISR_CH_0_2_DONE 0x11 /* channels 0, 2 done mask */
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#define TALITOS_ISR_CH_1_3_ERR 0x88 /* channels 1, 3 errors mask */
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#define TALITOS_ISR_CH_1_3_DONE 0x44 /* channels 1, 3 done mask */
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#define TALITOS_ISR_LO 0x1014
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#define TALITOS_ICR 0x1018 /* interrupt clear register */
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#define TALITOS_ICR_LO 0x101C
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/* channel register address stride */
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#define TALITOS_CH_BASE_OFFSET 0x1000 /* default channel map base */
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#define TALITOS_CH_STRIDE 0x100
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/* channel configuration register */
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#define TALITOS_CCCR 0x8
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#define TALITOS_CCCR_CONT 0x2 /* channel continue */
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#define TALITOS_CCCR_RESET 0x1 /* channel reset */
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#define TALITOS_CCCR_LO 0xc
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#define TALITOS_CCCR_LO_IWSE 0x80 /* chan. ICCR writeback enab. */
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#define TALITOS_CCCR_LO_EAE 0x20 /* extended address enable */
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#define TALITOS_CCCR_LO_CDWE 0x10 /* chan. done writeback enab. */
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#define TALITOS_CCCR_LO_NT 0x4 /* notification type */
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#define TALITOS_CCCR_LO_CDIE 0x2 /* channel done IRQ enable */
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/* CCPSR: channel pointer status register */
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#define TALITOS_CCPSR 0x10
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#define TALITOS_CCPSR_LO 0x14
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#define TALITOS_CCPSR_LO_DOF 0x8000 /* double FF write oflow error */
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#define TALITOS_CCPSR_LO_SOF 0x4000 /* single FF write oflow error */
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#define TALITOS_CCPSR_LO_MDTE 0x2000 /* master data transfer error */
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#define TALITOS_CCPSR_LO_SGDLZ 0x1000 /* s/g data len zero error */
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#define TALITOS_CCPSR_LO_FPZ 0x0800 /* fetch ptr zero error */
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#define TALITOS_CCPSR_LO_IDH 0x0400 /* illegal desc hdr error */
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#define TALITOS_CCPSR_LO_IEU 0x0200 /* invalid EU error */
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#define TALITOS_CCPSR_LO_EU 0x0100 /* EU error detected */
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#define TALITOS_CCPSR_LO_GB 0x0080 /* gather boundary error */
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#define TALITOS_CCPSR_LO_GRL 0x0040 /* gather return/length error */
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#define TALITOS_CCPSR_LO_SB 0x0020 /* scatter boundary error */
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#define TALITOS_CCPSR_LO_SRL 0x0010 /* scatter return/length error */
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/* channel fetch fifo register */
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#define TALITOS_FF 0x48
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#define TALITOS_FF_LO 0x4c
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/* current descriptor pointer register */
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#define TALITOS_CDPR 0x40
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#define TALITOS_CDPR_LO 0x44
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/* descriptor buffer register */
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#define TALITOS_DESCBUF 0x80
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#define TALITOS_DESCBUF_LO 0x84
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/* gather link table */
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#define TALITOS_GATHER 0xc0
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#define TALITOS_GATHER_LO 0xc4
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/* scatter link table */
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#define TALITOS_SCATTER 0xe0
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#define TALITOS_SCATTER_LO 0xe4
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/* execution unit interrupt status registers */
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#define TALITOS_DEUISR 0x2030 /* DES unit */
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#define TALITOS_DEUISR_LO 0x2034
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#define TALITOS_AESUISR 0x4030 /* AES unit */
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#define TALITOS_AESUISR_LO 0x4034
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#define TALITOS_MDEUISR 0x6030 /* message digest unit */
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#define TALITOS_MDEUISR_LO 0x6034
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#define TALITOS_MDEUICR 0x6038 /* interrupt control */
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#define TALITOS_MDEUICR_LO 0x603c
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#define TALITOS_MDEUICR_LO_ICE 0x4000 /* integrity check IRQ enable */
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#define TALITOS_AFEUISR 0x8030 /* arc4 unit */
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#define TALITOS_AFEUISR_LO 0x8034
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#define TALITOS_RNGUISR 0xa030 /* random number unit */
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#define TALITOS_RNGUISR_LO 0xa034
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#define TALITOS_RNGUSR 0xa028 /* rng status */
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#define TALITOS_RNGUSR_LO 0xa02c
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#define TALITOS_RNGUSR_LO_RD 0x1 /* reset done */
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#define TALITOS_RNGUSR_LO_OFL 0xff0000/* output FIFO length */
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#define TALITOS_RNGUDSR 0xa010 /* data size */
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#define TALITOS_RNGUDSR_LO 0xa014
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#define TALITOS_RNGU_FIFO 0xa800 /* output FIFO */
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#define TALITOS_RNGU_FIFO_LO 0xa804 /* output FIFO */
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#define TALITOS_RNGURCR 0xa018 /* reset control */
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#define TALITOS_RNGURCR_LO 0xa01c
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#define TALITOS_RNGURCR_LO_SR 0x1 /* software reset */
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#define TALITOS_PKEUISR 0xc030 /* public key unit */
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#define TALITOS_PKEUISR_LO 0xc034
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#define TALITOS_KEUISR 0xe030 /* kasumi unit */
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#define TALITOS_KEUISR_LO 0xe034
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#define TALITOS_CRCUISR 0xf030 /* cyclic redundancy check unit*/
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#define TALITOS_CRCUISR_LO 0xf034
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#define TALITOS_MDEU_CONTEXT_SIZE_MD5_SHA1_SHA256 0x28
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#define TALITOS_MDEU_CONTEXT_SIZE_SHA384_SHA512 0x48
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/*
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* talitos descriptor header (hdr) bits
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*/
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/* written back when done */
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#define DESC_HDR_DONE cpu_to_be32(0xff000000)
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#define DESC_HDR_LO_ICCR1_MASK cpu_to_be32(0x00180000)
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#define DESC_HDR_LO_ICCR1_PASS cpu_to_be32(0x00080000)
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#define DESC_HDR_LO_ICCR1_FAIL cpu_to_be32(0x00100000)
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/* primary execution unit select */
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#define DESC_HDR_SEL0_MASK cpu_to_be32(0xf0000000)
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#define DESC_HDR_SEL0_AFEU cpu_to_be32(0x10000000)
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#define DESC_HDR_SEL0_DEU cpu_to_be32(0x20000000)
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#define DESC_HDR_SEL0_MDEUA cpu_to_be32(0x30000000)
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#define DESC_HDR_SEL0_MDEUB cpu_to_be32(0xb0000000)
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#define DESC_HDR_SEL0_RNG cpu_to_be32(0x40000000)
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#define DESC_HDR_SEL0_PKEU cpu_to_be32(0x50000000)
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#define DESC_HDR_SEL0_AESU cpu_to_be32(0x60000000)
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#define DESC_HDR_SEL0_KEU cpu_to_be32(0x70000000)
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#define DESC_HDR_SEL0_CRCU cpu_to_be32(0x80000000)
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/* primary execution unit mode (MODE0) and derivatives */
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#define DESC_HDR_MODE0_ENCRYPT cpu_to_be32(0x00100000)
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#define DESC_HDR_MODE0_AESU_CBC cpu_to_be32(0x00200000)
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#define DESC_HDR_MODE0_DEU_CBC cpu_to_be32(0x00400000)
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#define DESC_HDR_MODE0_DEU_3DES cpu_to_be32(0x00200000)
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#define DESC_HDR_MODE0_MDEU_CONT cpu_to_be32(0x08000000)
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#define DESC_HDR_MODE0_MDEU_INIT cpu_to_be32(0x01000000)
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#define DESC_HDR_MODE0_MDEU_HMAC cpu_to_be32(0x00800000)
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#define DESC_HDR_MODE0_MDEU_PAD cpu_to_be32(0x00400000)
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#define DESC_HDR_MODE0_MDEU_SHA224 cpu_to_be32(0x00300000)
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#define DESC_HDR_MODE0_MDEU_MD5 cpu_to_be32(0x00200000)
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#define DESC_HDR_MODE0_MDEU_SHA256 cpu_to_be32(0x00100000)
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#define DESC_HDR_MODE0_MDEU_SHA1 cpu_to_be32(0x00000000)
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#define DESC_HDR_MODE0_MDEUB_SHA384 cpu_to_be32(0x00000000)
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#define DESC_HDR_MODE0_MDEUB_SHA512 cpu_to_be32(0x00200000)
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#define DESC_HDR_MODE0_MDEU_MD5_HMAC (DESC_HDR_MODE0_MDEU_MD5 | \
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DESC_HDR_MODE0_MDEU_HMAC)
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#define DESC_HDR_MODE0_MDEU_SHA256_HMAC (DESC_HDR_MODE0_MDEU_SHA256 | \
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DESC_HDR_MODE0_MDEU_HMAC)
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#define DESC_HDR_MODE0_MDEU_SHA1_HMAC (DESC_HDR_MODE0_MDEU_SHA1 | \
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DESC_HDR_MODE0_MDEU_HMAC)
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/* secondary execution unit select (SEL1) */
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#define DESC_HDR_SEL1_MASK cpu_to_be32(0x000f0000)
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#define DESC_HDR_SEL1_MDEUA cpu_to_be32(0x00030000)
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#define DESC_HDR_SEL1_MDEUB cpu_to_be32(0x000b0000)
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#define DESC_HDR_SEL1_CRCU cpu_to_be32(0x00080000)
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/* secondary execution unit mode (MODE1) and derivatives */
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#define DESC_HDR_MODE1_MDEU_CICV cpu_to_be32(0x00004000)
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#define DESC_HDR_MODE1_MDEU_INIT cpu_to_be32(0x00001000)
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#define DESC_HDR_MODE1_MDEU_HMAC cpu_to_be32(0x00000800)
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#define DESC_HDR_MODE1_MDEU_PAD cpu_to_be32(0x00000400)
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#define DESC_HDR_MODE1_MDEU_SHA224 cpu_to_be32(0x00000300)
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#define DESC_HDR_MODE1_MDEU_MD5 cpu_to_be32(0x00000200)
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#define DESC_HDR_MODE1_MDEU_SHA256 cpu_to_be32(0x00000100)
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#define DESC_HDR_MODE1_MDEU_SHA1 cpu_to_be32(0x00000000)
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#define DESC_HDR_MODE1_MDEUB_SHA384 cpu_to_be32(0x00000000)
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#define DESC_HDR_MODE1_MDEUB_SHA512 cpu_to_be32(0x00000200)
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#define DESC_HDR_MODE1_MDEU_MD5_HMAC (DESC_HDR_MODE1_MDEU_MD5 | \
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DESC_HDR_MODE1_MDEU_HMAC)
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#define DESC_HDR_MODE1_MDEU_SHA256_HMAC (DESC_HDR_MODE1_MDEU_SHA256 | \
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DESC_HDR_MODE1_MDEU_HMAC)
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#define DESC_HDR_MODE1_MDEU_SHA1_HMAC (DESC_HDR_MODE1_MDEU_SHA1 | \
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DESC_HDR_MODE1_MDEU_HMAC)
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#define DESC_HDR_MODE1_MDEU_SHA224_HMAC (DESC_HDR_MODE1_MDEU_SHA224 | \
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DESC_HDR_MODE1_MDEU_HMAC)
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#define DESC_HDR_MODE1_MDEUB_SHA384_HMAC (DESC_HDR_MODE1_MDEUB_SHA384 | \
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DESC_HDR_MODE1_MDEU_HMAC)
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#define DESC_HDR_MODE1_MDEUB_SHA512_HMAC (DESC_HDR_MODE1_MDEUB_SHA512 | \
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DESC_HDR_MODE1_MDEU_HMAC)
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/* direction of overall data flow (DIR) */
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#define DESC_HDR_DIR_INBOUND cpu_to_be32(0x00000002)
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/* request done notification (DN) */
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#define DESC_HDR_DONE_NOTIFY cpu_to_be32(0x00000001)
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/* descriptor types */
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#define DESC_HDR_TYPE_AESU_CTR_NONSNOOP cpu_to_be32(0 << 3)
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#define DESC_HDR_TYPE_IPSEC_ESP cpu_to_be32(1 << 3)
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#define DESC_HDR_TYPE_COMMON_NONSNOOP_NO_AFEU cpu_to_be32(2 << 3)
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#define DESC_HDR_TYPE_HMAC_SNOOP_NO_AFEU cpu_to_be32(4 << 3)
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/* link table extent field bits */
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#define DESC_PTR_LNKTBL_JUMP 0x80
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#define DESC_PTR_LNKTBL_RETURN 0x02
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#define DESC_PTR_LNKTBL_NEXT 0x01
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