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1ac758648b
Newer chips such as the 88E6390 have a VTU Page bit in the VTU VID register to specify a 13th bit for the VID. This can be used to support 8K VLANs. When dumping the whole VTU, all VID bits must be set to one, including this VTU Page bit. Add support for VID greater than 4095. Signed-off-by: Vivien Didelot <vivien.didelot@savoirfairelinux.com> Signed-off-by: David S. Miller <davem@davemloft.net>
387 lines
8.2 KiB
C
387 lines
8.2 KiB
C
/*
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* Marvell 88E6xxx VLAN [Spanning Tree] Translation Unit (VTU [STU]) support
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*
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* Copyright (c) 2008 Marvell Semiconductor
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* Copyright (c) 2015 CMC Electronics, Inc.
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* Copyright (c) 2017 Savoir-faire Linux, Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include "mv88e6xxx.h"
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#include "global1.h"
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/* Offset 0x02: VTU FID Register */
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static int mv88e6xxx_g1_vtu_fid_read(struct mv88e6xxx_chip *chip,
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struct mv88e6xxx_vtu_entry *entry)
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{
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u16 val;
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int err;
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err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_FID, &val);
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if (err)
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return err;
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entry->fid = val & GLOBAL_VTU_FID_MASK;
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return 0;
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}
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static int mv88e6xxx_g1_vtu_fid_write(struct mv88e6xxx_chip *chip,
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struct mv88e6xxx_vtu_entry *entry)
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{
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u16 val = entry->fid & GLOBAL_VTU_FID_MASK;
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return mv88e6xxx_g1_write(chip, GLOBAL_VTU_FID, val);
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}
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/* Offset 0x03: VTU SID Register */
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static int mv88e6xxx_g1_vtu_sid_read(struct mv88e6xxx_chip *chip,
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struct mv88e6xxx_vtu_entry *entry)
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{
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u16 val;
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int err;
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err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_SID, &val);
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if (err)
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return err;
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entry->sid = val & GLOBAL_VTU_SID_MASK;
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return 0;
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}
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static int mv88e6xxx_g1_vtu_sid_write(struct mv88e6xxx_chip *chip,
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struct mv88e6xxx_vtu_entry *entry)
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{
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u16 val = entry->sid & GLOBAL_VTU_SID_MASK;
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return mv88e6xxx_g1_write(chip, GLOBAL_VTU_SID, val);
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}
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/* Offset 0x05: VTU Operation Register */
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static int mv88e6xxx_g1_vtu_op_wait(struct mv88e6xxx_chip *chip)
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{
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return mv88e6xxx_g1_wait(chip, GLOBAL_VTU_OP, GLOBAL_VTU_OP_BUSY);
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}
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static int mv88e6xxx_g1_vtu_op(struct mv88e6xxx_chip *chip, u16 op)
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{
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int err;
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err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_OP, op);
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if (err)
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return err;
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return mv88e6xxx_g1_vtu_op_wait(chip);
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}
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/* Offset 0x06: VTU VID Register */
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static int mv88e6xxx_g1_vtu_vid_read(struct mv88e6xxx_chip *chip,
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struct mv88e6xxx_vtu_entry *entry)
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{
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u16 val;
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int err;
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err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_VID, &val);
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if (err)
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return err;
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entry->vid = val & 0xfff;
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if (val & GLOBAL_VTU_VID_PAGE)
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entry->vid |= 0x1000;
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entry->valid = !!(val & GLOBAL_VTU_VID_VALID);
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return 0;
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}
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static int mv88e6xxx_g1_vtu_vid_write(struct mv88e6xxx_chip *chip,
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struct mv88e6xxx_vtu_entry *entry)
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{
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u16 val = entry->vid & 0xfff;
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if (entry->vid & 0x1000)
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val |= GLOBAL_VTU_VID_PAGE;
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if (entry->valid)
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val |= GLOBAL_VTU_VID_VALID;
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return mv88e6xxx_g1_write(chip, GLOBAL_VTU_VID, val);
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}
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/* Offset 0x07: VTU/STU Data Register 1
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* Offset 0x08: VTU/STU Data Register 2
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* Offset 0x09: VTU/STU Data Register 3
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*/
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static int mv88e6185_g1_vtu_data_read(struct mv88e6xxx_chip *chip,
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struct mv88e6xxx_vtu_entry *entry)
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{
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u16 regs[3];
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int i;
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/* Read all 3 VTU/STU Data registers */
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for (i = 0; i < 3; ++i) {
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u16 *reg = ®s[i];
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int err;
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err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
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if (err)
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return err;
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}
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/* Extract MemberTag and PortState data */
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for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
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unsigned int member_offset = (i % 4) * 4;
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unsigned int state_offset = member_offset + 2;
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entry->member[i] = (regs[i / 4] >> member_offset) & 0x3;
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entry->state[i] = (regs[i / 4] >> state_offset) & 0x3;
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}
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return 0;
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}
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static int mv88e6185_g1_vtu_data_write(struct mv88e6xxx_chip *chip,
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struct mv88e6xxx_vtu_entry *entry)
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{
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u16 regs[3] = { 0 };
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int i;
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/* Insert MemberTag and PortState data */
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for (i = 0; i < mv88e6xxx_num_ports(chip); ++i) {
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unsigned int member_offset = (i % 4) * 4;
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unsigned int state_offset = member_offset + 2;
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regs[i / 4] |= (entry->member[i] & 0x3) << member_offset;
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regs[i / 4] |= (entry->state[i] & 0x3) << state_offset;
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}
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/* Write all 3 VTU/STU Data registers */
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for (i = 0; i < 3; ++i) {
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u16 reg = regs[i];
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int err;
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err = mv88e6xxx_g1_write(chip, GLOBAL_VTU_DATA_0_3 + i, reg);
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if (err)
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return err;
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}
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return 0;
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}
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/* VLAN Translation Unit Operations */
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static int mv88e6xxx_g1_vtu_stu_getnext(struct mv88e6xxx_chip *chip,
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struct mv88e6xxx_vtu_entry *entry)
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{
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int err;
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err = mv88e6xxx_g1_vtu_sid_write(chip, entry);
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if (err)
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return err;
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err = mv88e6xxx_g1_vtu_op(chip, GLOBAL_VTU_OP_STU_GET_NEXT);
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if (err)
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return err;
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err = mv88e6xxx_g1_vtu_sid_read(chip, entry);
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if (err)
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return err;
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return mv88e6xxx_g1_vtu_vid_read(chip, entry);
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}
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static int mv88e6xxx_g1_vtu_stu_get(struct mv88e6xxx_chip *chip,
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struct mv88e6xxx_vtu_entry *vtu)
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{
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struct mv88e6xxx_vtu_entry stu;
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int err;
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err = mv88e6xxx_g1_vtu_sid_read(chip, vtu);
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if (err)
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return err;
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stu.sid = vtu->sid - 1;
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err = mv88e6xxx_g1_vtu_stu_getnext(chip, &stu);
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if (err)
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return err;
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if (stu.sid != vtu->sid || !stu.valid)
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return -EINVAL;
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return 0;
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}
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static int mv88e6xxx_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
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struct mv88e6xxx_vtu_entry *entry)
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{
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int err;
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err = mv88e6xxx_g1_vtu_op_wait(chip);
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if (err)
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return err;
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/* To get the next higher active VID, the VTU GetNext operation can be
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* started again without setting the VID registers since it already
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* contains the last VID.
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*
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* To save a few hardware accesses and abstract this to the caller,
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* write the VID only once, when the entry is given as invalid.
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*/
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if (!entry->valid) {
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err = mv88e6xxx_g1_vtu_vid_write(chip, entry);
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if (err)
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return err;
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}
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err = mv88e6xxx_g1_vtu_op(chip, GLOBAL_VTU_OP_VTU_GET_NEXT);
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if (err)
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return err;
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return mv88e6xxx_g1_vtu_vid_read(chip, entry);
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}
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int mv88e6185_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
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struct mv88e6xxx_vtu_entry *entry)
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{
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u16 val;
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int err;
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err = mv88e6xxx_g1_vtu_getnext(chip, entry);
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if (err)
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return err;
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if (entry->valid) {
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err = mv88e6185_g1_vtu_data_read(chip, entry);
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if (err)
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return err;
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/* VTU DBNum[3:0] are located in VTU Operation 3:0
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* VTU DBNum[7:4] are located in VTU Operation 11:8
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*/
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err = mv88e6xxx_g1_read(chip, GLOBAL_VTU_OP, &val);
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if (err)
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return err;
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entry->fid = val & 0x000f;
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entry->fid |= (val & 0x0f00) >> 4;
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}
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return 0;
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}
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int mv88e6352_g1_vtu_getnext(struct mv88e6xxx_chip *chip,
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struct mv88e6xxx_vtu_entry *entry)
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{
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int err;
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/* Fetch VLAN MemberTag data from the VTU */
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err = mv88e6xxx_g1_vtu_getnext(chip, entry);
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if (err)
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return err;
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if (entry->valid) {
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/* Fetch (and mask) VLAN PortState data from the STU */
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err = mv88e6xxx_g1_vtu_stu_get(chip, entry);
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if (err)
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return err;
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err = mv88e6185_g1_vtu_data_read(chip, entry);
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if (err)
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return err;
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err = mv88e6xxx_g1_vtu_fid_read(chip, entry);
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if (err)
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return err;
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}
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return 0;
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}
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int mv88e6185_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
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struct mv88e6xxx_vtu_entry *entry)
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{
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u16 op = GLOBAL_VTU_OP_VTU_LOAD_PURGE;
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int err;
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err = mv88e6xxx_g1_vtu_op_wait(chip);
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if (err)
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return err;
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err = mv88e6xxx_g1_vtu_vid_write(chip, entry);
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if (err)
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return err;
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if (entry->valid) {
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err = mv88e6185_g1_vtu_data_write(chip, entry);
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if (err)
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return err;
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/* VTU DBNum[3:0] are located in VTU Operation 3:0
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* VTU DBNum[7:4] are located in VTU Operation 11:8
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*/
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op |= entry->fid & 0x000f;
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op |= (entry->fid & 0x00f0) << 8;
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}
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return mv88e6xxx_g1_vtu_op(chip, op);
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}
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int mv88e6352_g1_vtu_loadpurge(struct mv88e6xxx_chip *chip,
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struct mv88e6xxx_vtu_entry *entry)
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{
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int err;
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err = mv88e6xxx_g1_vtu_op_wait(chip);
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if (err)
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return err;
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err = mv88e6xxx_g1_vtu_vid_write(chip, entry);
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if (err)
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return err;
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if (entry->valid) {
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/* Write MemberTag and PortState data */
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err = mv88e6185_g1_vtu_data_write(chip, entry);
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if (err)
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return err;
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err = mv88e6xxx_g1_vtu_sid_write(chip, entry);
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if (err)
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return err;
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/* Load STU entry */
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err = mv88e6xxx_g1_vtu_op(chip, GLOBAL_VTU_OP_STU_LOAD_PURGE);
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if (err)
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return err;
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err = mv88e6xxx_g1_vtu_fid_write(chip, entry);
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if (err)
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return err;
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}
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/* Load/Purge VTU entry */
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return mv88e6xxx_g1_vtu_op(chip, GLOBAL_VTU_OP_VTU_LOAD_PURGE);
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}
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int mv88e6xxx_g1_vtu_flush(struct mv88e6xxx_chip *chip)
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{
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int err;
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err = mv88e6xxx_g1_vtu_op_wait(chip);
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if (err)
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return err;
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return mv88e6xxx_g1_vtu_op(chip, GLOBAL_VTU_OP_FLUSH_ALL);
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}
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