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036e9cf356
Allow usage of gpio-ranges with the rockchip gpio controller. The driver already had support for this since it has been added to the mainline kernel in the first place. Acked-by: Rob Herring <robh@kernel.org> Signed-off-by: Sebastian Reichel <sebastian.reichel@collabora.com> Reviewed-by: Heiko Stuebner <heiko@sntech.de> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
89 lines
1.7 KiB
YAML
89 lines
1.7 KiB
YAML
# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/gpio/rockchip,gpio-bank.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Rockchip GPIO bank
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maintainers:
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- Heiko Stuebner <heiko@sntech.de>
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properties:
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compatible:
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enum:
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- rockchip,gpio-bank
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- rockchip,rk3188-gpio-bank0
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reg:
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maxItems: 1
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interrupts:
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maxItems: 1
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clocks:
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minItems: 1
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items:
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- description: APB interface clock source
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- description: GPIO debounce reference clock source
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gpio-ranges: true
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gpio-controller: true
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gpio-line-names: true
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"#gpio-cells":
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const: 2
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interrupt-controller: true
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"#interrupt-cells":
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const: 2
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required:
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- compatible
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- reg
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- interrupts
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- clocks
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- gpio-controller
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- "#gpio-cells"
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- interrupt-controller
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- "#interrupt-cells"
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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pinctrl: pinctrl {
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#address-cells = <1>;
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#size-cells = <1>;
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ranges;
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gpio0: gpio@2000a000 {
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compatible = "rockchip,rk3188-gpio-bank0";
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reg = <0x2000a000 0x100>;
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interrupts = <GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_gates8 9>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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gpio1: gpio@2003c000 {
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compatible = "rockchip,gpio-bank";
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reg = <0x2003c000 0x100>;
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interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clk_gates8 10>;
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gpio-controller;
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#gpio-cells = <2>;
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interrupt-controller;
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#interrupt-cells = <2>;
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};
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};
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