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1a472c9dba
Core kernel doesn't track the page size of the VA range that we are invalidating. Hence we end up flushing TLB for the entire mm here. Later patches will improve this. We also don't flush page walk cache separetly instead use RIC=2 when flushing TLB, because we do a MMU gather flush after freeing page table. MMU_NO_CONTEXT is updated for hash. Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
101 lines
2.4 KiB
C
101 lines
2.4 KiB
C
#ifndef _ASM_POWERPC_BOOK3S_64_TLBFLUSH_HASH_H
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#define _ASM_POWERPC_BOOK3S_64_TLBFLUSH_HASH_H
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/*
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* TLB flushing for 64-bit hash-MMU CPUs
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*/
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#include <linux/percpu.h>
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#include <asm/page.h>
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#define PPC64_TLB_BATCH_NR 192
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struct ppc64_tlb_batch {
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int active;
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unsigned long index;
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struct mm_struct *mm;
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real_pte_t pte[PPC64_TLB_BATCH_NR];
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unsigned long vpn[PPC64_TLB_BATCH_NR];
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unsigned int psize;
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int ssize;
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};
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DECLARE_PER_CPU(struct ppc64_tlb_batch, ppc64_tlb_batch);
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extern void __flush_tlb_pending(struct ppc64_tlb_batch *batch);
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#define __HAVE_ARCH_ENTER_LAZY_MMU_MODE
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static inline void arch_enter_lazy_mmu_mode(void)
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{
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struct ppc64_tlb_batch *batch;
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if (radix_enabled())
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return;
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batch = this_cpu_ptr(&ppc64_tlb_batch);
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batch->active = 1;
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}
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static inline void arch_leave_lazy_mmu_mode(void)
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{
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struct ppc64_tlb_batch *batch;
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if (radix_enabled())
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return;
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batch = this_cpu_ptr(&ppc64_tlb_batch);
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if (batch->index)
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__flush_tlb_pending(batch);
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batch->active = 0;
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}
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#define arch_flush_lazy_mmu_mode() do {} while (0)
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extern void flush_hash_page(unsigned long vpn, real_pte_t pte, int psize,
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int ssize, unsigned long flags);
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extern void flush_hash_range(unsigned long number, int local);
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extern void flush_hash_hugepage(unsigned long vsid, unsigned long addr,
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pmd_t *pmdp, unsigned int psize, int ssize,
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unsigned long flags);
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static inline void hash__local_flush_tlb_mm(struct mm_struct *mm)
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{
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}
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static inline void hash__flush_tlb_mm(struct mm_struct *mm)
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{
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}
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static inline void hash__local_flush_tlb_page(struct vm_area_struct *vma,
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unsigned long vmaddr)
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{
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}
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static inline void hash__flush_tlb_page(struct vm_area_struct *vma,
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unsigned long vmaddr)
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{
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}
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static inline void hash__flush_tlb_page_nohash(struct vm_area_struct *vma,
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unsigned long vmaddr)
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{
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}
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static inline void hash__flush_tlb_range(struct vm_area_struct *vma,
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unsigned long start, unsigned long end)
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{
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}
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static inline void hash__flush_tlb_kernel_range(unsigned long start,
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unsigned long end)
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{
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}
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struct mmu_gather;
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extern void hash__tlb_flush(struct mmu_gather *tlb);
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/* Private function for use by PCI IO mapping code */
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extern void __flush_hash_table_range(struct mm_struct *mm, unsigned long start,
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unsigned long end);
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extern void flush_tlb_pmd_range(struct mm_struct *mm, pmd_t *pmd,
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unsigned long addr);
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#endif /* _ASM_POWERPC_BOOK3S_64_TLBFLUSH_HASH_H */
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