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f025d9d993
The Kendryte K210 SoC CLINT is compatible with Sifive clint v0 (sifive,clint0). Fix the Kendryte K210 device tree clint entry to be inline with the sifive timer definition documented in Documentation/devicetree/bindings/timer/sifive,clint.yaml. The device tree clint entry is renamed similarly to u-boot device tree definition to improve compatibility with u-boot defined device tree. To ensure correct initialization, the interrup-cells attribute is added and the interrupt-extended attribute definition fixed. This fixes boot failures with Kendryte K210 SoC boards. Note that the clock referenced is kept as K210_CLK_ACLK, which does not necessarilly match the clint MTIME increment rate. This however does not seem to cause any problem for now. Signed-off-by: Damien Le Moal <damien.lemoal@wdc.com> Signed-off-by: Palmer Dabbelt <palmerdabbelt@google.com>
125 lines
3.1 KiB
Text
125 lines
3.1 KiB
Text
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Copyright (C) 2019 Sean Anderson <seanga2@gmail.com>
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* Copyright (C) 2020 Western Digital Corporation or its affiliates.
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*/
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#include <dt-bindings/clock/k210-clk.h>
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/ {
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/*
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* Although the K210 is a 64-bit CPU, the address bus is only 32-bits
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* wide, and the upper half of all addresses is ignored.
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*/
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "kendryte,k210";
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aliases {
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serial0 = &uarths0;
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};
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/*
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* The K210 has an sv39 MMU following the priviledge specification v1.9.
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* Since this is a non-ratified draft specification, the kernel does not
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* support it and the K210 support enabled only for the !MMU case.
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* Be consistent with this by setting the CPUs MMU type to "none".
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*/
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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timebase-frequency = <7800000>;
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cpu0: cpu@0 {
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device_type = "cpu";
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reg = <0>;
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compatible = "kendryte,k210", "sifive,rocket0", "riscv";
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riscv,isa = "rv64imafdc";
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mmu-type = "none";
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i-cache-size = <0x8000>;
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i-cache-block-size = <64>;
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d-cache-size = <0x8000>;
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d-cache-block-size = <64>;
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clocks = <&sysctl K210_CLK_CPU>;
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clock-frequency = <390000000>;
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cpu0_intc: interrupt-controller {
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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cpu1: cpu@1 {
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device_type = "cpu";
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reg = <1>;
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compatible = "kendryte,k210", "sifive,rocket0", "riscv";
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riscv,isa = "rv64imafdc";
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mmu-type = "none";
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i-cache-size = <0x8000>;
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i-cache-block-size = <64>;
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d-cache-size = <0x8000>;
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d-cache-block-size = <64>;
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clocks = <&sysctl K210_CLK_CPU>;
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clock-frequency = <390000000>;
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cpu1_intc: interrupt-controller {
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "riscv,cpu-intc";
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};
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};
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};
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sram: memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 0x400000>,
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<0x80400000 0x200000>,
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<0x80600000 0x200000>;
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reg-names = "sram0", "sram1", "aisram";
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};
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clocks {
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in0: oscillator {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <26000000>;
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};
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "kendryte,k210-soc", "simple-bus";
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ranges;
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interrupt-parent = <&plic0>;
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sysctl: sysctl@50440000 {
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compatible = "kendryte,k210-sysctl", "simple-mfd";
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reg = <0x50440000 0x1000>;
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#clock-cells = <1>;
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};
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clint0: clint@2000000 {
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#interrupt-cells = <1>;
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compatible = "riscv,clint0";
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reg = <0x2000000 0xC000>;
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interrupts-extended = <&cpu0_intc 3 &cpu0_intc 7
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&cpu1_intc 3 &cpu1_intc 7>;
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clocks = <&sysctl K210_CLK_ACLK>;
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};
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plic0: interrupt-controller@c000000 {
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "kendryte,k210-plic0", "riscv,plic0";
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reg = <0xC000000 0x4000000>;
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interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 0xffffffff>,
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<&cpu1_intc 11>, <&cpu1_intc 0xffffffff>;
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riscv,ndev = <65>;
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riscv,max-priority = <7>;
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};
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uarths0: serial@38000000 {
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compatible = "kendryte,k210-uarths", "sifive,uart0";
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reg = <0x38000000 0x1000>;
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interrupts = <33>;
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clocks = <&sysctl K210_CLK_CPU>;
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};
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};
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};
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