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1512f908f3
Apple's PCIe controller requires clocks to be configured in order to bring up the hardware. Add the register pokes required to do so. Adapted from Corellium's driver via Mark Kettenis's U-Boot patches. Co-developed-by: Stan Skowronek <stan@corellium.com> Link: https://lore.kernel.org/r/20210929163847.2807812-6-maz@kernel.org Signed-off-by: Stan Skowronek <stan@corellium.com> Signed-off-by: Alyssa Rosenzweig <alyssa@rosenzweig.io> Signed-off-by: Marc Zyngier <maz@kernel.org> Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com> Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
284 lines
8 KiB
C
284 lines
8 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* PCIe host bridge driver for Apple system-on-chips.
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*
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* The HW is ECAM compliant, so once the controller is initialized,
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* the driver mostly deals MSI mapping and handling of per-port
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* interrupts (INTx, management and error signals).
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*
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* Initialization requires enabling power and clocks, along with a
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* number of register pokes.
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*
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* Copyright (C) 2021 Alyssa Rosenzweig <alyssa@rosenzweig.io>
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* Copyright (C) 2021 Google LLC
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* Copyright (C) 2021 Corellium LLC
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* Copyright (C) 2021 Mark Kettenis <kettenis@openbsd.org>
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*
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* Author: Alyssa Rosenzweig <alyssa@rosenzweig.io>
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* Author: Marc Zyngier <maz@kernel.org>
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*/
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#include <linux/gpio/consumer.h>
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#include <linux/kernel.h>
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#include <linux/iopoll.h>
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#include <linux/irqdomain.h>
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#include <linux/module.h>
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#include <linux/msi.h>
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#include <linux/of_irq.h>
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#include <linux/pci-ecam.h>
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#define CORE_RC_PHYIF_CTL 0x00024
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#define CORE_RC_PHYIF_CTL_RUN BIT(0)
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#define CORE_RC_PHYIF_STAT 0x00028
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#define CORE_RC_PHYIF_STAT_REFCLK BIT(4)
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#define CORE_RC_CTL 0x00050
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#define CORE_RC_CTL_RUN BIT(0)
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#define CORE_RC_STAT 0x00058
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#define CORE_RC_STAT_READY BIT(0)
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#define CORE_FABRIC_STAT 0x04000
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#define CORE_FABRIC_STAT_MASK 0x001F001F
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#define CORE_LANE_CFG(port) (0x84000 + 0x4000 * (port))
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#define CORE_LANE_CFG_REFCLK0REQ BIT(0)
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#define CORE_LANE_CFG_REFCLK1 BIT(1)
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#define CORE_LANE_CFG_REFCLK0ACK BIT(2)
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#define CORE_LANE_CFG_REFCLKEN (BIT(9) | BIT(10))
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#define CORE_LANE_CTL(port) (0x84004 + 0x4000 * (port))
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#define CORE_LANE_CTL_CFGACC BIT(15)
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#define PORT_LTSSMCTL 0x00080
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#define PORT_LTSSMCTL_START BIT(0)
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#define PORT_INTSTAT 0x00100
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#define PORT_INT_TUNNEL_ERR 31
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#define PORT_INT_CPL_TIMEOUT 23
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#define PORT_INT_RID2SID_MAPERR 22
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#define PORT_INT_CPL_ABORT 21
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#define PORT_INT_MSI_BAD_DATA 19
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#define PORT_INT_MSI_ERR 18
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#define PORT_INT_REQADDR_GT32 17
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#define PORT_INT_AF_TIMEOUT 15
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#define PORT_INT_LINK_DOWN 14
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#define PORT_INT_LINK_UP 12
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#define PORT_INT_LINK_BWMGMT 11
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#define PORT_INT_AER_MASK (15 << 4)
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#define PORT_INT_PORT_ERR 4
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#define PORT_INT_INTx(i) i
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#define PORT_INT_INTx_MASK 15
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#define PORT_INTMSK 0x00104
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#define PORT_INTMSKSET 0x00108
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#define PORT_INTMSKCLR 0x0010c
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#define PORT_MSICFG 0x00124
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#define PORT_MSICFG_EN BIT(0)
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#define PORT_MSICFG_L2MSINUM_SHIFT 4
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#define PORT_MSIBASE 0x00128
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#define PORT_MSIBASE_1_SHIFT 16
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#define PORT_MSIADDR 0x00168
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#define PORT_LINKSTS 0x00208
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#define PORT_LINKSTS_UP BIT(0)
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#define PORT_LINKSTS_BUSY BIT(2)
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#define PORT_LINKCMDSTS 0x00210
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#define PORT_OUTS_NPREQS 0x00284
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#define PORT_OUTS_NPREQS_REQ BIT(24)
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#define PORT_OUTS_NPREQS_CPL BIT(16)
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#define PORT_RXWR_FIFO 0x00288
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#define PORT_RXWR_FIFO_HDR GENMASK(15, 10)
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#define PORT_RXWR_FIFO_DATA GENMASK(9, 0)
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#define PORT_RXRD_FIFO 0x0028C
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#define PORT_RXRD_FIFO_REQ GENMASK(6, 0)
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#define PORT_OUTS_CPLS 0x00290
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#define PORT_OUTS_CPLS_SHRD GENMASK(14, 8)
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#define PORT_OUTS_CPLS_WAIT GENMASK(6, 0)
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#define PORT_APPCLK 0x00800
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#define PORT_APPCLK_EN BIT(0)
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#define PORT_APPCLK_CGDIS BIT(8)
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#define PORT_STATUS 0x00804
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#define PORT_STATUS_READY BIT(0)
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#define PORT_REFCLK 0x00810
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#define PORT_REFCLK_EN BIT(0)
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#define PORT_REFCLK_CGDIS BIT(8)
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#define PORT_PERST 0x00814
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#define PORT_PERST_OFF BIT(0)
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#define PORT_RID2SID(i16) (0x00828 + 4 * (i16))
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#define PORT_RID2SID_VALID BIT(31)
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#define PORT_RID2SID_SID_SHIFT 16
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#define PORT_RID2SID_BUS_SHIFT 8
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#define PORT_RID2SID_DEV_SHIFT 3
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#define PORT_RID2SID_FUNC_SHIFT 0
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#define PORT_OUTS_PREQS_HDR 0x00980
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#define PORT_OUTS_PREQS_HDR_MASK GENMASK(9, 0)
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#define PORT_OUTS_PREQS_DATA 0x00984
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#define PORT_OUTS_PREQS_DATA_MASK GENMASK(15, 0)
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#define PORT_TUNCTRL 0x00988
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#define PORT_TUNCTRL_PERST_ON BIT(0)
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#define PORT_TUNCTRL_PERST_ACK_REQ BIT(1)
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#define PORT_TUNSTAT 0x0098c
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#define PORT_TUNSTAT_PERST_ON BIT(0)
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#define PORT_TUNSTAT_PERST_ACK_PEND BIT(1)
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#define PORT_PREFMEM_ENABLE 0x00994
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struct apple_pcie {
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struct device *dev;
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void __iomem *base;
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};
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struct apple_pcie_port {
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struct apple_pcie *pcie;
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struct device_node *np;
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void __iomem *base;
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int idx;
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};
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static void rmw_set(u32 set, void __iomem *addr)
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{
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writel_relaxed(readl_relaxed(addr) | set, addr);
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}
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static void rmw_clear(u32 clr, void __iomem *addr)
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{
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writel_relaxed(readl_relaxed(addr) & ~clr, addr);
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}
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static int apple_pcie_setup_refclk(struct apple_pcie *pcie,
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struct apple_pcie_port *port)
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{
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u32 stat;
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int res;
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res = readl_relaxed_poll_timeout(pcie->base + CORE_RC_PHYIF_STAT, stat,
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stat & CORE_RC_PHYIF_STAT_REFCLK,
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100, 50000);
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if (res < 0)
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return res;
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rmw_set(CORE_LANE_CTL_CFGACC, pcie->base + CORE_LANE_CTL(port->idx));
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rmw_set(CORE_LANE_CFG_REFCLK0REQ, pcie->base + CORE_LANE_CFG(port->idx));
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res = readl_relaxed_poll_timeout(pcie->base + CORE_LANE_CFG(port->idx),
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stat, stat & CORE_LANE_CFG_REFCLK0ACK,
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100, 50000);
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if (res < 0)
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return res;
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rmw_set(CORE_LANE_CFG_REFCLK1, pcie->base + CORE_LANE_CFG(port->idx));
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res = readl_relaxed_poll_timeout(pcie->base + CORE_LANE_CFG(port->idx),
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stat, stat & CORE_LANE_CFG_REFCLK1,
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100, 50000);
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if (res < 0)
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return res;
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rmw_clear(CORE_LANE_CTL_CFGACC, pcie->base + CORE_LANE_CTL(port->idx));
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rmw_set(CORE_LANE_CFG_REFCLKEN, pcie->base + CORE_LANE_CFG(port->idx));
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rmw_set(PORT_REFCLK_EN, port->base + PORT_REFCLK);
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return 0;
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}
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static int apple_pcie_setup_port(struct apple_pcie *pcie,
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struct device_node *np)
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{
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struct platform_device *platform = to_platform_device(pcie->dev);
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struct apple_pcie_port *port;
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struct gpio_desc *reset;
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u32 stat, idx;
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int ret;
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reset = gpiod_get_from_of_node(np, "reset-gpios", 0,
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GPIOD_OUT_LOW, "#PERST");
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if (IS_ERR(reset))
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return PTR_ERR(reset);
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port = devm_kzalloc(pcie->dev, sizeof(*port), GFP_KERNEL);
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if (!port)
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return -ENOMEM;
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ret = of_property_read_u32_index(np, "reg", 0, &idx);
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if (ret)
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return ret;
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/* Use the first reg entry to work out the port index */
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port->idx = idx >> 11;
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port->pcie = pcie;
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port->np = np;
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port->base = devm_platform_ioremap_resource(platform, port->idx + 2);
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if (IS_ERR(port->base))
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return PTR_ERR(port->base);
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rmw_set(PORT_APPCLK_EN, port->base + PORT_APPCLK);
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ret = apple_pcie_setup_refclk(pcie, port);
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if (ret < 0)
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return ret;
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rmw_set(PORT_PERST_OFF, port->base + PORT_PERST);
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gpiod_set_value(reset, 1);
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ret = readl_relaxed_poll_timeout(port->base + PORT_STATUS, stat,
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stat & PORT_STATUS_READY, 100, 250000);
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if (ret < 0) {
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dev_err(pcie->dev, "port %pOF ready wait timeout\n", np);
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return ret;
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}
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writel_relaxed(PORT_LTSSMCTL_START, port->base + PORT_LTSSMCTL);
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return 0;
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}
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static int apple_pcie_init(struct pci_config_window *cfg)
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{
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struct device *dev = cfg->parent;
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struct platform_device *platform = to_platform_device(dev);
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struct device_node *of_port;
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struct apple_pcie *pcie;
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int ret;
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pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL);
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if (!pcie)
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return -ENOMEM;
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pcie->dev = dev;
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pcie->base = devm_platform_ioremap_resource(platform, 1);
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if (IS_ERR(pcie->base))
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return PTR_ERR(pcie->base);
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for_each_child_of_node(dev->of_node, of_port) {
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ret = apple_pcie_setup_port(pcie, of_port);
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if (ret) {
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dev_err(pcie->dev, "Port %pOF setup fail: %d\n", of_port, ret);
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of_node_put(of_port);
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return ret;
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}
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}
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return 0;
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}
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static const struct pci_ecam_ops apple_pcie_cfg_ecam_ops = {
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.init = apple_pcie_init,
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.pci_ops = {
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.map_bus = pci_ecam_map_bus,
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.read = pci_generic_config_read,
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.write = pci_generic_config_write,
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}
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};
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static const struct of_device_id apple_pcie_of_match[] = {
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{ .compatible = "apple,pcie", .data = &apple_pcie_cfg_ecam_ops },
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{ }
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};
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MODULE_DEVICE_TABLE(of, apple_pcie_of_match);
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static struct platform_driver apple_pcie_driver = {
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.probe = pci_host_common_probe,
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.driver = {
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.name = "pcie-apple",
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.of_match_table = apple_pcie_of_match,
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.suppress_bind_attrs = true,
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},
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};
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module_platform_driver(apple_pcie_driver);
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MODULE_LICENSE("GPL v2");
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