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12a6727dee
This patch is to add one sysfs file -- "pp_od_clk_voltage" for
Raven/Raven2/Picasso APU, which is only used by dGPU like VEGA10.
This sysfs file supports the feature to modify gfx engine clock(Mhz units), it can
be used to configure the min value and the max value for gfx clock limited in the
safe range.
Command guide:
echo "s level clock" > pp_od_clk_voltage
s - adjust teh sclk level
level - 0 or 1, "0" represents the min value, "1" represents the max value
clock - the clock value(Mhz units), like 400, 800 or 1200, the value must be within the
OD_RANGE limits.
Example:
$ cat pp_od_clk_voltage
OD_SCLK:
0: 200Mhz
1: 1400Mhz
OD_RANGE:
SCLK: 200MHz 1400MHz
$ echo "s 0 600" > pp_od_clk_voltage
$ echo "s 1 1000" > pp_od_clk_voltage
$ cat pp_od_clk_voltage
OD_SCLK:
0: 600Mhz
1: 1000Mhz
OD_RANGE:
SCLK: 200MHz 1400MHz
Signed-off-by: Xiaojian Du <Xiaojian.Du@amd.com>
Reviewed-by: Kevin Wang <kevin1.wang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
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|---|---|---|
| .. | ||
| asic_reg | ||
| ivsrcid | ||
| amd_acpi.h | ||
| amd_pcie.h | ||
| amd_pcie_helpers.h | ||
| amd_shared.h | ||
| arct_ip_offset.h | ||
| atom-bits.h | ||
| atom-names.h | ||
| atom-types.h | ||
| atombios.h | ||
| atomfirmware.h | ||
| atomfirmwareid.h | ||
| cgs_common.h | ||
| cik_structs.h | ||
| discovery.h | ||
| displayobject.h | ||
| dm_pp_interface.h | ||
| kgd_kfd_interface.h | ||
| kgd_pp_interface.h | ||
| navi10_enum.h | ||
| navi10_ip_offset.h | ||
| navi12_ip_offset.h | ||
| navi14_ip_offset.h | ||
| pptable.h | ||
| renoir_ip_offset.h | ||
| sienna_cichlid_ip_offset.h | ||
| soc15_hw_ip.h | ||
| soc15_ih_clientid.h | ||
| v9_structs.h | ||
| v10_structs.h | ||
| vega10_enum.h | ||
| vega10_ip_offset.h | ||
| vega20_ip_offset.h | ||
| vi_structs.h | ||