Eugeni Dodonov 12a13a3389 drm/i915: add WR PLL programming table ... This table is used for programming WR PLL clocks, used by HDMI and DVI outputs. I split it into a separate patch to simplify the HDMI enabling patch which was getting huge. Note that this table is a temporary solution for WR PLL programming. It will be reworked into a more exact algorithm at a later stage. But for now, it provides the most accurate clock setting solution, so we use it here. Signed-off-by: Eugeni Dodonov <eugeni.dodonov@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>		2012-05-19 22:39:51 +02:00
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drm	drm/i915: add WR PLL programming table	2012-05-19 22:39:51 +02:00
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vga	vga: fix build when fbdev is a module	2012-04-24 09:50:21 +01:00
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