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	Add the description for imx-scu gpio subnode. Signed-off-by: Shenwei Wang <shenwei.wang@nxp.com> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Signed-off-by: Bartosz Golaszewski <brgl@bgdev.pl>
		
			
				
	
	
		
			215 lines
		
	
	
	
		
			6.4 KiB
		
	
	
	
		
			YAML
		
	
	
	
	
	
			
		
		
	
	
			215 lines
		
	
	
	
		
			6.4 KiB
		
	
	
	
		
			YAML
		
	
	
	
	
	
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/firmware/fsl,scu.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: NXP i.MX System Controller Firmware (SCFW)
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maintainers:
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  - Dong Aisheng <aisheng.dong@nxp.com>
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description:
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  The System Controller Firmware (SCFW) is a low-level system function
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  which runs on a dedicated Cortex-M core to provide power, clock, and
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  resource management. It exists on some i.MX8 processors. e.g. i.MX8QM
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  (QM, QP), and i.MX8QX (QXP, DX).
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  The AP communicates with the SC using a multi-ported MU module found
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  in the LSIO subsystem. The current definition of this MU module provides
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  5 remote AP connections to the SC to support up to 5 execution environments
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  (TZ, HV, standard Linux, etc.). The SC side of this MU module interfaces
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  with the LSIO DSC IP bus. The SC firmware will communicate with this MU
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  using the MSI bus.
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properties:
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  compatible:
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    const: fsl,imx-scu
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  clock-controller:
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    description:
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      Clock controller node that provides the clocks controlled by the SCU
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    $ref: /schemas/clock/fsl,scu-clk.yaml
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  gpio:
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    description:
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      Control the GPIO PINs on SCU domain over the firmware APIs
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    $ref: /schemas/gpio/fsl,imx8qxp-sc-gpio.yaml
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  ocotp:
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    description:
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      OCOTP controller node provided by the SCU
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    $ref: /schemas/nvmem/fsl,scu-ocotp.yaml
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  keys:
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    description:
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      Keys provided by the SCU
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    $ref: /schemas/input/fsl,scu-key.yaml
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  mboxes:
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    description:
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      A list of phandles of TX MU channels followed by a list of phandles of
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      RX MU channels. The list may include at the end one more optional MU
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      channel for general interrupt. The number of expected tx and rx
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      channels is 1 TX and 1 RX channels if MU instance is "fsl,imx8-mu-scu"
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      compatible, 4 TX and 4 RX channels otherwise. All MU channels must be
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      within the same MU instance. Cross instances are not allowed. The MU
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      instance can only be one of LSIO MU0~M4 for imx8qxp and imx8qm. Users
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      need to ensure that one is used that does not conflict with other
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      execution environments such as ATF.
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    oneOf:
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      - items:
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          - description: TX0 MU channel
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          - description: RX0 MU channel
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      - items:
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          - description: TX0 MU channel
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          - description: RX0 MU channel
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          - description: optional MU channel for general interrupt
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      - items:
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          - description: TX0 MU channel
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          - description: TX1 MU channel
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          - description: TX2 MU channel
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          - description: TX3 MU channel
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          - description: RX0 MU channel
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          - description: RX1 MU channel
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          - description: RX2 MU channel
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          - description: RX3 MU channel
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      - items:
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          - description: TX0 MU channel
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          - description: TX1 MU channel
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          - description: TX2 MU channel
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          - description: TX3 MU channel
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          - description: RX0 MU channel
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          - description: RX1 MU channel
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          - description: RX2 MU channel
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          - description: RX3 MU channel
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          - description: optional MU channel for general interrupt
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  mbox-names:
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    oneOf:
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      - items:
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          - const: tx0
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          - const: rx0
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      - items:
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          - const: tx0
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          - const: rx0
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          - const: gip3
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      - items:
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          - const: tx0
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          - const: tx1
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          - const: tx2
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          - const: tx3
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          - const: rx0
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          - const: rx1
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          - const: rx2
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          - const: rx3
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      - items:
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          - const: tx0
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          - const: tx1
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          - const: tx2
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          - const: tx3
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          - const: rx0
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          - const: rx1
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          - const: rx2
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          - const: rx3
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          - const: gip3
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  pinctrl:
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    description:
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      Pin controller provided by the SCU
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    $ref: /schemas/pinctrl/fsl,scu-pinctrl.yaml
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  power-controller:
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    description:
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      Power domains controller node that provides the power domains
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      controlled by the SCU
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    $ref: /schemas/power/fsl,scu-pd.yaml
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  rtc:
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    description:
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      RTC controller provided by the SCU
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    $ref: /schemas/rtc/fsl,scu-rtc.yaml
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  thermal-sensor:
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    description:
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      Thermal sensor provided by the SCU
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    $ref: /schemas/thermal/fsl,scu-thermal.yaml
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  watchdog:
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    description:
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      Watchdog controller provided by the SCU
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    $ref: /schemas/watchdog/fsl,scu-wdt.yaml
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required:
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  - compatible
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  - mbox-names
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  - mboxes
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additionalProperties: false
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examples:
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  - |
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    #include <dt-bindings/firmware/imx/rsrc.h>
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    #include <dt-bindings/input/input.h>
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    #include <dt-bindings/pinctrl/pads-imx8qxp.h>
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    firmware {
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        system-controller {
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            compatible = "fsl,imx-scu";
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            mbox-names = "tx0", "tx1", "tx2", "tx3",
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                         "rx0", "rx1", "rx2", "rx3",
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                         "gip3";
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            mboxes = <&lsio_mu1 0 0 &lsio_mu1 0 1 &lsio_mu1 0 2 &lsio_mu1 0 3
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                      &lsio_mu1 1 0 &lsio_mu1 1 1 &lsio_mu1 1 2 &lsio_mu1 1 3
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                      &lsio_mu1 3 3>;
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            clock-controller {
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                compatible = "fsl,imx8qxp-clk", "fsl,scu-clk";
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                #clock-cells = <2>;
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            };
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            pinctrl {
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                compatible = "fsl,imx8qxp-iomuxc";
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                pinctrl_lpuart0: lpuart0grp {
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                    fsl,pins = <
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                        IMX8QXP_UART0_RX_ADMA_UART0_RX   0x06000020
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                        IMX8QXP_UART0_TX_ADMA_UART0_TX   0x06000020
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                    >;
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                };
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            };
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            ocotp {
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                compatible = "fsl,imx8qxp-scu-ocotp";
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                #address-cells = <1>;
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                #size-cells = <1>;
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                fec_mac0: mac@2c4 {
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                    reg = <0x2c4 6>;
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                };
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            };
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            power-controller {
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                compatible = "fsl,imx8qxp-scu-pd", "fsl,scu-pd";
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                #power-domain-cells = <1>;
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            };
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            rtc {
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                compatible = "fsl,imx8qxp-sc-rtc";
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            };
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            keys {
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                compatible = "fsl,imx8qxp-sc-key", "fsl,imx-sc-key";
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                linux,keycodes = <KEY_POWER>;
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            };
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            watchdog {
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                compatible = "fsl,imx8qxp-sc-wdt", "fsl,imx-sc-wdt";
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                timeout-sec = <60>;
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            };
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            thermal-sensor {
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                compatible = "fsl,imx8qxp-sc-thermal", "fsl,imx-sc-thermal";
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                #thermal-sensor-cells = <1>;
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            };
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        };
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    };
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