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10a8d9b906
The clocks might need to modify their parent clocks. In order to make that possible, give them access to the parent clock being evaluated, and to a pointer to the parent rate so that they can modify it if needed. Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com> Signed-off-by: Chen-Yu Tsai <wens@csie.org>
149 lines
3.7 KiB
C
149 lines
3.7 KiB
C
/*
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* Copyright (C) 2016 Maxime Ripard
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* Maxime Ripard <maxime.ripard@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License as
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* published by the Free Software Foundation; either version 2 of
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* the License, or (at your option) any later version.
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*/
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#include <linux/clk-provider.h>
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#include "ccu_gate.h"
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#include "ccu_div.h"
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static unsigned long ccu_div_round_rate(struct ccu_mux_internal *mux,
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struct clk_hw *parent,
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unsigned long *parent_rate,
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unsigned long rate,
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void *data)
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{
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struct ccu_div *cd = data;
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unsigned long val;
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/*
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* We can't use divider_round_rate that assumes that there's
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* several parents, while we might be called to evaluate
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* several different parents.
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*/
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val = divider_get_val(rate, *parent_rate, cd->div.table, cd->div.width,
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cd->div.flags);
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return divider_recalc_rate(&cd->common.hw, *parent_rate, val,
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cd->div.table, cd->div.flags);
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}
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static void ccu_div_disable(struct clk_hw *hw)
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{
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struct ccu_div *cd = hw_to_ccu_div(hw);
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return ccu_gate_helper_disable(&cd->common, cd->enable);
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}
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static int ccu_div_enable(struct clk_hw *hw)
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{
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struct ccu_div *cd = hw_to_ccu_div(hw);
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return ccu_gate_helper_enable(&cd->common, cd->enable);
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}
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static int ccu_div_is_enabled(struct clk_hw *hw)
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{
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struct ccu_div *cd = hw_to_ccu_div(hw);
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return ccu_gate_helper_is_enabled(&cd->common, cd->enable);
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}
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static unsigned long ccu_div_recalc_rate(struct clk_hw *hw,
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unsigned long parent_rate)
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{
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struct ccu_div *cd = hw_to_ccu_div(hw);
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unsigned long val;
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u32 reg;
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reg = readl(cd->common.base + cd->common.reg);
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val = reg >> cd->div.shift;
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val &= (1 << cd->div.width) - 1;
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ccu_mux_helper_adjust_parent_for_prediv(&cd->common, &cd->mux, -1,
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&parent_rate);
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return divider_recalc_rate(hw, parent_rate, val, cd->div.table,
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cd->div.flags);
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}
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static int ccu_div_determine_rate(struct clk_hw *hw,
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struct clk_rate_request *req)
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{
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struct ccu_div *cd = hw_to_ccu_div(hw);
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if (clk_hw_get_num_parents(hw) == 1) {
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req->rate = divider_round_rate(hw, req->rate,
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&req->best_parent_rate,
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cd->div.table,
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cd->div.width,
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cd->div.flags);
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req->best_parent_hw = clk_hw_get_parent(hw);
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return 0;
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}
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return ccu_mux_helper_determine_rate(&cd->common, &cd->mux,
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req, ccu_div_round_rate, cd);
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}
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static int ccu_div_set_rate(struct clk_hw *hw, unsigned long rate,
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unsigned long parent_rate)
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{
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struct ccu_div *cd = hw_to_ccu_div(hw);
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unsigned long flags;
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unsigned long val;
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u32 reg;
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ccu_mux_helper_adjust_parent_for_prediv(&cd->common, &cd->mux, -1,
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&parent_rate);
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val = divider_get_val(rate, parent_rate, cd->div.table, cd->div.width,
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cd->div.flags);
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spin_lock_irqsave(cd->common.lock, flags);
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reg = readl(cd->common.base + cd->common.reg);
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reg &= ~GENMASK(cd->div.width + cd->div.shift - 1, cd->div.shift);
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writel(reg | (val << cd->div.shift),
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cd->common.base + cd->common.reg);
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spin_unlock_irqrestore(cd->common.lock, flags);
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return 0;
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}
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static u8 ccu_div_get_parent(struct clk_hw *hw)
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{
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struct ccu_div *cd = hw_to_ccu_div(hw);
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return ccu_mux_helper_get_parent(&cd->common, &cd->mux);
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}
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static int ccu_div_set_parent(struct clk_hw *hw, u8 index)
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{
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struct ccu_div *cd = hw_to_ccu_div(hw);
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return ccu_mux_helper_set_parent(&cd->common, &cd->mux, index);
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}
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const struct clk_ops ccu_div_ops = {
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.disable = ccu_div_disable,
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.enable = ccu_div_enable,
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.is_enabled = ccu_div_is_enabled,
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.get_parent = ccu_div_get_parent,
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.set_parent = ccu_div_set_parent,
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.determine_rate = ccu_div_determine_rate,
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.recalc_rate = ccu_div_recalc_rate,
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.set_rate = ccu_div_set_rate,
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};
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