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0ee958e102
This patch introduces a new SMP implementation for systems implementing the MIPS Coherent Processing System architecture. The kernel will make use of the Coherence Manager, Cluster Power Controller & Global Interrupt Controller in order to detect, bring up & make use of other cores in the system. SMTC is not supported, so only a single TC per VPE in the system is used. That is, this option enables an SMVP style setup but across multiple cores. Signed-off-by: Paul Burton <paul.burton@imgtec.com> Cc: linux-mips@linux-mips.org Patchwork: https://patchwork.linux-mips.org/patch/6362/ Patchwork: https://patchwork.linux-mips.org/patch/6611/ Patchwork: https://patchwork.linux-mips.org/patch/6651/ Patchwork: https://patchwork.linux-mips.org/patch/6652/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
112 lines
2.2 KiB
C
112 lines
2.2 KiB
C
/*
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* This file is subject to the terms and conditions of the GNU General
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* Public License. See the file "COPYING" in the main directory of this
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* archive for more details.
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*
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* Copyright (C) 2000 - 2001 by Kanoj Sarcar (kanoj@sgi.com)
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* Copyright (C) 2000 - 2001 by Silicon Graphics, Inc.
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* Copyright (C) 2000, 2001, 2002 Ralf Baechle
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* Copyright (C) 2000, 2001 Broadcom Corporation
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*/
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#ifndef __ASM_SMP_OPS_H
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#define __ASM_SMP_OPS_H
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#include <linux/errno.h>
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#ifdef CONFIG_SMP
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#include <linux/cpumask.h>
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struct task_struct;
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struct plat_smp_ops {
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void (*send_ipi_single)(int cpu, unsigned int action);
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void (*send_ipi_mask)(const struct cpumask *mask, unsigned int action);
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void (*init_secondary)(void);
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void (*smp_finish)(void);
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void (*cpus_done)(void);
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void (*boot_secondary)(int cpu, struct task_struct *idle);
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void (*smp_setup)(void);
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void (*prepare_cpus)(unsigned int max_cpus);
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#ifdef CONFIG_HOTPLUG_CPU
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int (*cpu_disable)(void);
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void (*cpu_die)(unsigned int cpu);
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#endif
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};
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extern void register_smp_ops(struct plat_smp_ops *ops);
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static inline void plat_smp_setup(void)
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{
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extern struct plat_smp_ops *mp_ops; /* private */
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mp_ops->smp_setup();
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}
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#else /* !CONFIG_SMP */
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struct plat_smp_ops;
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static inline void plat_smp_setup(void)
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{
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/* UP, nothing to do ... */
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}
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static inline void register_smp_ops(struct plat_smp_ops *ops)
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{
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}
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#endif /* !CONFIG_SMP */
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extern void gic_send_ipi_single(int cpu, unsigned int action);
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extern void gic_send_ipi_mask(const struct cpumask *mask, unsigned int action);
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static inline int register_up_smp_ops(void)
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{
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#ifdef CONFIG_SMP_UP
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extern struct plat_smp_ops up_smp_ops;
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register_smp_ops(&up_smp_ops);
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return 0;
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#else
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return -ENODEV;
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#endif
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}
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static inline int register_cmp_smp_ops(void)
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{
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#ifdef CONFIG_MIPS_CMP
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extern struct plat_smp_ops cmp_smp_ops;
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register_smp_ops(&cmp_smp_ops);
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return 0;
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#else
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return -ENODEV;
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#endif
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}
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static inline int register_vsmp_smp_ops(void)
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{
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#ifdef CONFIG_MIPS_MT_SMP
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extern struct plat_smp_ops vsmp_smp_ops;
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register_smp_ops(&vsmp_smp_ops);
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return 0;
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#else
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return -ENODEV;
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#endif
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}
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#ifdef CONFIG_MIPS_CPS
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extern int register_cps_smp_ops(void);
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#else
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static inline int register_cps_smp_ops(void)
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{
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return -ENODEV;
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}
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#endif
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#endif /* __ASM_SMP_OPS_H */
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