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![]() The HOST1X_CHANNEL_DMAEND is an offset relative to the value written to the HOST1X_CHANNEL_DMASTART register, but it is currently treated as an absolute address. This can cause SMMU faults if the CDMA fetches past a pushbuffer's IOMMU mapping. Properly setting the DMAEND prevents the CDMA from fetching beyond that address and avoid such issues. This is currently not observed because a whole (almost) page of essentially scratch space absorbs any excessive prefetching by CDMA. However, changing the number of slots in the push buffer can trigger these SMMU faults. Signed-off-by: Thierry Reding <treding@nvidia.com> |
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.. | ||
cdma_hw.c | ||
channel_hw.c | ||
debug_hw.c | ||
debug_hw_1x01.c | ||
debug_hw_1x06.c | ||
host1x01.c | ||
host1x01.h | ||
host1x01_hardware.h | ||
host1x02.c | ||
host1x02.h | ||
host1x02_hardware.h | ||
host1x04.c | ||
host1x04.h | ||
host1x04_hardware.h | ||
host1x05.c | ||
host1x05.h | ||
host1x05_hardware.h | ||
host1x06.c | ||
host1x06.h | ||
host1x06_hardware.h | ||
host1x07.c | ||
host1x07.h | ||
host1x07_hardware.h | ||
hw_host1x01_channel.h | ||
hw_host1x01_sync.h | ||
hw_host1x01_uclass.h | ||
hw_host1x02_channel.h | ||
hw_host1x02_sync.h | ||
hw_host1x02_uclass.h | ||
hw_host1x04_channel.h | ||
hw_host1x04_sync.h | ||
hw_host1x04_uclass.h | ||
hw_host1x05_channel.h | ||
hw_host1x05_sync.h | ||
hw_host1x05_uclass.h | ||
hw_host1x06_channel.h | ||
hw_host1x06_hypervisor.h | ||
hw_host1x06_uclass.h | ||
hw_host1x06_vm.h | ||
hw_host1x07_channel.h | ||
hw_host1x07_hypervisor.h | ||
hw_host1x07_uclass.h | ||
hw_host1x07_vm.h | ||
intr_hw.c | ||
syncpt_hw.c |