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0d8295ed97
The Scalar Crypto specification defines Zk as a shorthand for the Zkn, Zkr and Zkt extensions. The same follows for both Zkn, Zks and Zbk, which are all shorthands for various other extensions. The detailed breakdown can be found in their dt-binding entries. Since Zkn also implies the Zbkb, Zbkc and Zbkx extensions, simply passing "zk" through a DT should enable all of Zbkb, Zbkc, Zbkx, Zkn, Zkr and Zkt. For example, setting the "riscv,isa" DT property to "rv64imafdc_zk" should generate the following cpuinfo output: "rv64imafdc_zicntr_zicsr_zifencei_zihpm_zbkb_zbkc_zbkx_zknd_zkne_zknh_zkr_zkt" riscv_isa_ext_data grows a pair of new members, to permit setting the relevant bits for "bundled" extensions, both while parsing the ISA string and the new dedicated extension properties. Co-developed-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Evan Green <evan@rivosinc.com> Signed-off-by: Clément Léger <cleger@rivosinc.com> Acked-by: Conor Dooley <conor.dooley@microchip.com> Link: https://lore.kernel.org/r/20231114141256.126749-4-cleger@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
138 lines
3.1 KiB
C
138 lines
3.1 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright 2022-2023 Rivos, Inc
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*/
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#ifndef _ASM_CPUFEATURE_H
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#define _ASM_CPUFEATURE_H
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#include <linux/bitmap.h>
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#include <linux/jump_label.h>
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#include <asm/hwcap.h>
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#include <asm/alternative-macros.h>
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#include <asm/errno.h>
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/*
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* These are probed via a device_initcall(), via either the SBI or directly
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* from the corresponding CSRs.
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*/
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struct riscv_cpuinfo {
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unsigned long mvendorid;
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unsigned long marchid;
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unsigned long mimpid;
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};
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struct riscv_isainfo {
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DECLARE_BITMAP(isa, RISCV_ISA_EXT_MAX);
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};
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DECLARE_PER_CPU(struct riscv_cpuinfo, riscv_cpuinfo);
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DECLARE_PER_CPU(long, misaligned_access_speed);
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/* Per-cpu ISA extensions. */
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extern struct riscv_isainfo hart_isa[NR_CPUS];
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void riscv_user_isa_enable(void);
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#ifdef CONFIG_RISCV_MISALIGNED
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bool unaligned_ctl_available(void);
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bool check_unaligned_access_emulated(int cpu);
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void unaligned_emulation_finish(void);
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#else
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static inline bool unaligned_ctl_available(void)
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{
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return false;
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}
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static inline bool check_unaligned_access_emulated(int cpu)
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{
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return false;
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}
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static inline void unaligned_emulation_finish(void) {}
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#endif
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unsigned long riscv_get_elf_hwcap(void);
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struct riscv_isa_ext_data {
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const unsigned int id;
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const char *name;
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const char *property;
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const unsigned int *subset_ext_ids;
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const unsigned int subset_ext_size;
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};
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extern const struct riscv_isa_ext_data riscv_isa_ext[];
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extern const size_t riscv_isa_ext_count;
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extern bool riscv_isa_fallback;
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unsigned long riscv_isa_extension_base(const unsigned long *isa_bitmap);
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bool __riscv_isa_extension_available(const unsigned long *isa_bitmap, unsigned int bit);
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#define riscv_isa_extension_available(isa_bitmap, ext) \
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__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_##ext)
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static __always_inline bool
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riscv_has_extension_likely(const unsigned long ext)
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{
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compiletime_assert(ext < RISCV_ISA_EXT_MAX,
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"ext must be < RISCV_ISA_EXT_MAX");
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if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {
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asm_volatile_goto(
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ALTERNATIVE("j %l[l_no]", "nop", 0, %[ext], 1)
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:
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: [ext] "i" (ext)
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:
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: l_no);
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} else {
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if (!__riscv_isa_extension_available(NULL, ext))
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goto l_no;
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}
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return true;
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l_no:
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return false;
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}
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static __always_inline bool
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riscv_has_extension_unlikely(const unsigned long ext)
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{
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compiletime_assert(ext < RISCV_ISA_EXT_MAX,
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"ext must be < RISCV_ISA_EXT_MAX");
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if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE)) {
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asm_volatile_goto(
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ALTERNATIVE("nop", "j %l[l_yes]", 0, %[ext], 1)
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:
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: [ext] "i" (ext)
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:
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: l_yes);
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} else {
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if (__riscv_isa_extension_available(NULL, ext))
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goto l_yes;
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}
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return false;
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l_yes:
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return true;
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}
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static __always_inline bool riscv_cpu_has_extension_likely(int cpu, const unsigned long ext)
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{
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if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_likely(ext))
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return true;
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return __riscv_isa_extension_available(hart_isa[cpu].isa, ext);
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}
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static __always_inline bool riscv_cpu_has_extension_unlikely(int cpu, const unsigned long ext)
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{
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if (IS_ENABLED(CONFIG_RISCV_ALTERNATIVE) && riscv_has_extension_unlikely(ext))
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return true;
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return __riscv_isa_extension_available(hart_isa[cpu].isa, ext);
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}
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#endif
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