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076437c9e3
Signed-off-by: Dmitry Baryshkov <dmitry.baryshkov@linaro.org> Reviewed-by: Abhinav Kumar <abhinavk@codeaurora.org> Tested-by: Stephen Boyd <swboyd@chromium.org> # on sc7180 lazor Link: https://lore.kernel.org/r/20210331105735.3690009-9-dmitry.baryshkov@linaro.org Signed-off-by: Rob Clark <robdclark@chromium.org>
62 lines
1.3 KiB
C
62 lines
1.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only */
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/*
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* Copyright (c) 2012-2015, The Linux Foundation. All rights reserved.
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*/
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#ifndef __DSI_PLL_H__
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#define __DSI_PLL_H__
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#include <linux/clk-provider.h>
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#include <linux/delay.h>
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#include "dsi.h"
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#define NUM_DSI_CLOCKS_MAX 6
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struct msm_dsi_pll {
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struct clk_hw clk_hw;
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bool pll_on;
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bool state_saved;
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const struct msm_dsi_phy_cfg *cfg;
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};
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#define hw_clk_to_pll(x) container_of(x, struct msm_dsi_pll, clk_hw)
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static inline void pll_write(void __iomem *reg, u32 data)
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{
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msm_writel(data, reg);
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}
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static inline u32 pll_read(const void __iomem *reg)
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{
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return msm_readl(reg);
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}
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static inline void pll_write_udelay(void __iomem *reg, u32 data, u32 delay_us)
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{
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pll_write(reg, data);
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udelay(delay_us);
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}
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static inline void pll_write_ndelay(void __iomem *reg, u32 data, u32 delay_ns)
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{
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pll_write((reg), data);
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ndelay(delay_ns);
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}
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/*
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* DSI PLL Helper functions
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*/
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/* clock callbacks */
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long msm_dsi_pll_helper_clk_round_rate(struct clk_hw *hw,
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unsigned long rate, unsigned long *parent_rate);
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int msm_dsi_pll_helper_clk_prepare(struct clk_hw *hw);
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void msm_dsi_pll_helper_clk_unprepare(struct clk_hw *hw);
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/* misc */
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void msm_dsi_pll_helper_unregister_clks(struct platform_device *pdev,
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struct clk **clks, u32 num_clks);
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#endif /* __DSI_PLL_H__ */
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