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0181f6f19c
The ocelot switch driver used to ignore ports which do not have a phy-handle property and not probe those, but this is not quite ok since it is valid to not have a phy-handle property if there is a fixed-link. It seems that checking for a phy-handle was a proxy for the proper check which is for the status, but that doesn't make a lot of sense, since the ocelot driver already iterates using for_each_available_child_of_node which skips the disabled ports, so I have no idea. Anyway, a widespread pattern in device trees is for a SoC dtsi to disable by default all hardware, and let board dts files enable what is used. So let's do that and enable only the ports with a phy-handle in the pcb120 and pcb123 device tree files. Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
125 lines
2.1 KiB
Text
125 lines
2.1 KiB
Text
// SPDX-License-Identifier: (GPL-2.0 OR MIT)
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/* Copyright (c) 2017 Microsemi Corporation */
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/dts-v1/;
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/interrupt-controller/irq.h>
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#include <dt-bindings/phy/phy-ocelot-serdes.h>
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#include "ocelot.dtsi"
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/ {
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compatible = "mscc,ocelot-pcb120", "mscc,ocelot";
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chosen {
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stdout-path = "serial0:115200n8";
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x0e000000>;
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};
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};
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&gpio {
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phy_int_pins: phy_int_pins {
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pins = "GPIO_4";
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function = "gpio";
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};
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phy_load_save_pins: phy_load_save_pins {
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pins = "GPIO_10";
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function = "ptp2";
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};
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};
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&mdio0 {
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status = "okay";
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};
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&mdio1 {
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status = "okay";
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pinctrl-names = "default";
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pinctrl-0 = <&miim1>, <&phy_int_pins>, <&phy_load_save_pins>;
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phy7: ethernet-phy@0 {
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reg = <0>;
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interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gpio>;
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load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
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};
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phy6: ethernet-phy@1 {
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reg = <1>;
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interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gpio>;
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load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
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};
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phy5: ethernet-phy@2 {
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reg = <2>;
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interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gpio>;
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load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
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};
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phy4: ethernet-phy@3 {
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reg = <3>;
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interrupts = <4 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-parent = <&gpio>;
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load-save-gpios = <&gpio 10 GPIO_ACTIVE_HIGH>;
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};
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};
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&port0 {
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status = "okay";
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phy-handle = <&phy0>;
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};
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&port1 {
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status = "okay";
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phy-handle = <&phy1>;
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};
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&port2 {
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status = "okay";
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phy-handle = <&phy2>;
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};
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&port3 {
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status = "okay";
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phy-handle = <&phy3>;
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};
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&port4 {
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status = "okay";
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phy-handle = <&phy7>;
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phy-mode = "sgmii";
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phys = <&serdes 4 SERDES1G(2)>;
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};
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&port5 {
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status = "okay";
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phy-handle = <&phy4>;
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phy-mode = "sgmii";
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phys = <&serdes 5 SERDES1G(5)>;
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};
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&port6 {
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status = "okay";
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phy-handle = <&phy6>;
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phy-mode = "sgmii";
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phys = <&serdes 6 SERDES1G(3)>;
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};
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&port9 {
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status = "okay";
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phy-handle = <&phy5>;
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phy-mode = "sgmii";
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phys = <&serdes 9 SERDES1G(4)>;
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};
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&uart0 {
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status = "okay";
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};
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&uart2 {
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status = "okay";
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};
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