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ea1413e5b5
Add support for OpenRISC in the rseq selftests. OpenRISC is 32-bit
only.
Tested this with:
Compiler: gcc version 14.2.0 (GCC)
Binutils: GNU assembler version 2.43.1 (or1k-smh-linux-gnu) using BFD version (GNU Binutils) 2.43.1.20241207
Linux: Linux buildroot 6.13.0-rc2-00005-g1fa73dd6c2d3-dirty #213 SMP Sat Dec 28 22:18:39 GMT 2024 openrisc GNU/Linux
Glibc: 2024-12-13 e4e49583d9 Stafford Horne or1k: Update libm-test-ulps
Signed-off-by: Stafford Horne <shorne@gmail.com>
Reviewed-by: Mathieu Desnoyers <mathieu.desnoyers@efficios.com>
Acked-by: Shuah Khan <skhan@linuxfoundation.org>
181 lines
6.1 KiB
C
181 lines
6.1 KiB
C
/* SPDX-License-Identifier: LGPL-2.1 OR MIT */
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/*
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* Select the instruction "l.nop 0x35" as the RSEQ_SIG.
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*/
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#define RSEQ_SIG 0x15000035
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#define rseq_smp_mb() __asm__ __volatile__ ("l.msync" ::: "memory")
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#define rseq_smp_rmb() rseq_smp_mb()
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#define rseq_smp_wmb() rseq_smp_mb()
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#define RSEQ_ASM_TMP_REG_1 "r31"
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#define RSEQ_ASM_TMP_REG_2 "r29"
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#define RSEQ_ASM_TMP_REG_3 "r27"
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#define RSEQ_ASM_TMP_REG_4 "r25"
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#define rseq_smp_load_acquire(p) \
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__extension__ ({ \
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rseq_unqual_scalar_typeof(*(p)) ____p1 = RSEQ_READ_ONCE(*(p)); \
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rseq_smp_mb(); \
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____p1; \
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})
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#define rseq_smp_acquire__after_ctrl_dep() rseq_smp_rmb()
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#define rseq_smp_store_release(p, v) \
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do { \
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rseq_smp_mb(); \
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RSEQ_WRITE_ONCE(*(p), v); \
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} while (0)
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#define __RSEQ_ASM_DEFINE_TABLE(label, version, flags, start_ip, \
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post_commit_offset, abort_ip) \
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".pushsection __rseq_cs, \"aw\"\n" \
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".balign 32\n" \
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__rseq_str(label) ":\n" \
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".long " __rseq_str(version) ", " __rseq_str(flags) "\n" \
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".long 0x0, " __rseq_str(start_ip) ", " \
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"0x0, " __rseq_str(post_commit_offset) ", " \
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"0x0, " __rseq_str(abort_ip) "\n" \
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".popsection\n\t" \
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".pushsection __rseq_cs_ptr_array, \"aw\"\n" \
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".long 0x0, " __rseq_str(label) "b\n" \
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".popsection\n"
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#define RSEQ_ASM_DEFINE_TABLE(label, start_ip, post_commit_ip, abort_ip) \
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__RSEQ_ASM_DEFINE_TABLE(label, 0x0, 0x0, start_ip, \
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((post_commit_ip) - (start_ip)), abort_ip)
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/*
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* Exit points of a rseq critical section consist of all instructions outside
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* of the critical section where a critical section can either branch to or
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* reach through the normal course of its execution. The abort IP and the
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* post-commit IP are already part of the __rseq_cs section and should not be
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* explicitly defined as additional exit points. Knowing all exit points is
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* useful to assist debuggers stepping over the critical section.
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*/
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#define RSEQ_ASM_DEFINE_EXIT_POINT(start_ip, exit_ip) \
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".pushsection __rseq_exit_point_array, \"aw\"\n" \
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".long 0x0, " __rseq_str(start_ip) ", 0x0, " __rseq_str(exit_ip) "\n" \
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".popsection\n"
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#define RSEQ_ASM_STORE_RSEQ_CS(label, cs_label, rseq_cs) \
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RSEQ_INJECT_ASM(1) \
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"l.movhi " RSEQ_ASM_TMP_REG_1 ", hi(" __rseq_str(cs_label) ")\n"\
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"l.ori " RSEQ_ASM_TMP_REG_1 ", " RSEQ_ASM_TMP_REG_1 \
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", lo(" __rseq_str(cs_label) ")\n"\
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"l.sw %[" __rseq_str(rseq_cs) "], " RSEQ_ASM_TMP_REG_1 "\n" \
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__rseq_str(label) ":\n"
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#define RSEQ_ASM_DEFINE_ABORT(label, abort_label) \
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"l.j 222f\n" \
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" l.nop\n" \
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".balign 4\n" \
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".long " __rseq_str(RSEQ_SIG) "\n" \
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__rseq_str(label) ":\n" \
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"l.j %l[" __rseq_str(abort_label) "]\n" \
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" l.nop\n" \
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"222:\n"
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#define RSEQ_ASM_OP_STORE(var, value) \
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"l.sw %[" __rseq_str(var) "], %[" __rseq_str(value) "]\n"
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#define RSEQ_ASM_OP_CMPEQ(var, expect, label) \
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"l.lwz " RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(var) "]\n" \
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"l.sfne " RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(expect) "]\n" \
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"l.bf " __rseq_str(label) "\n" \
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" l.nop\n"
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#define RSEQ_ASM_OP_CMPNE(var, expect, label) \
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"l.lwz " RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(var) "]\n" \
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"l.sfeq " RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(expect) "]\n" \
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"l.bf " __rseq_str(label) "\n" \
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" l.nop\n"
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#define RSEQ_ASM_CMP_CPU_ID(cpu_id, current_cpu_id, label) \
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RSEQ_INJECT_ASM(2) \
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RSEQ_ASM_OP_CMPEQ(current_cpu_id, cpu_id, label)
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#define RSEQ_ASM_OP_R_LOAD(var) \
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"l.lwz " RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(var) "]\n"
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#define RSEQ_ASM_OP_R_STORE(var) \
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"l.sw %[" __rseq_str(var) "], " RSEQ_ASM_TMP_REG_1 "\n"
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#define RSEQ_ASM_OP_R_LOAD_OFF(offset) \
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"l.lwz " RSEQ_ASM_TMP_REG_1 ", " \
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"%[" __rseq_str(offset) "](" RSEQ_ASM_TMP_REG_1 ")\n"
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#define RSEQ_ASM_OP_R_ADD(count) \
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"l.add " RSEQ_ASM_TMP_REG_1 ", " RSEQ_ASM_TMP_REG_1 \
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", %[" __rseq_str(count) "]\n"
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#define RSEQ_ASM_OP_FINAL_STORE(var, value, post_commit_label) \
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RSEQ_ASM_OP_STORE(var, value) \
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__rseq_str(post_commit_label) ":\n"
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#define RSEQ_ASM_OP_FINAL_STORE_RELEASE(var, value, post_commit_label) \
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"l.msync\n" \
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RSEQ_ASM_OP_STORE(var, value) \
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__rseq_str(post_commit_label) ":\n"
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#define RSEQ_ASM_OP_R_FINAL_STORE(var, post_commit_label) \
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"l.sw %[" __rseq_str(var) "], " RSEQ_ASM_TMP_REG_1 "\n" \
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__rseq_str(post_commit_label) ":\n"
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#define RSEQ_ASM_OP_R_BAD_MEMCPY(dst, src, len) \
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"l.sfeq %[" __rseq_str(len) "], r0\n" \
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"l.bf 333f\n" \
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" l.nop\n" \
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"l.ori " RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(len) "], 0\n" \
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"l.ori " RSEQ_ASM_TMP_REG_2 ", %[" __rseq_str(src) "], 0\n" \
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"l.ori " RSEQ_ASM_TMP_REG_3 ", %[" __rseq_str(dst) "], 0\n" \
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"222:\n" \
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"l.lbz " RSEQ_ASM_TMP_REG_4 ", 0(" RSEQ_ASM_TMP_REG_2 ")\n" \
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"l.sb 0(" RSEQ_ASM_TMP_REG_3 "), " RSEQ_ASM_TMP_REG_4 "\n" \
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"l.addi " RSEQ_ASM_TMP_REG_1 ", " RSEQ_ASM_TMP_REG_1 ", -1\n" \
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"l.addi " RSEQ_ASM_TMP_REG_2 ", " RSEQ_ASM_TMP_REG_2 ", 1\n" \
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"l.addi " RSEQ_ASM_TMP_REG_3 ", " RSEQ_ASM_TMP_REG_3 ", 1\n" \
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"l.sfne " RSEQ_ASM_TMP_REG_1 ", r0\n" \
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"l.bf 222b\n" \
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" l.nop\n" \
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"333:\n"
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#define RSEQ_ASM_OP_R_DEREF_ADDV(ptr, off, inc, post_commit_label) \
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"l.ori " RSEQ_ASM_TMP_REG_1 ", %[" __rseq_str(ptr) "], 0\n" \
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RSEQ_ASM_OP_R_ADD(off) \
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"l.lwz " RSEQ_ASM_TMP_REG_1 ", 0(" RSEQ_ASM_TMP_REG_1 ")\n" \
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RSEQ_ASM_OP_R_ADD(inc) \
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__rseq_str(post_commit_label) ":\n"
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/* Per-cpu-id indexing. */
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#define RSEQ_TEMPLATE_CPU_ID
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#define RSEQ_TEMPLATE_MO_RELAXED
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#include "rseq-or1k-bits.h"
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#undef RSEQ_TEMPLATE_MO_RELAXED
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#define RSEQ_TEMPLATE_MO_RELEASE
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#include "rseq-or1k-bits.h"
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#undef RSEQ_TEMPLATE_MO_RELEASE
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#undef RSEQ_TEMPLATE_CPU_ID
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/* Per-mm-cid indexing. */
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#define RSEQ_TEMPLATE_MM_CID
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#define RSEQ_TEMPLATE_MO_RELAXED
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#include "rseq-or1k-bits.h"
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#undef RSEQ_TEMPLATE_MO_RELAXED
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#define RSEQ_TEMPLATE_MO_RELEASE
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#include "rseq-or1k-bits.h"
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#undef RSEQ_TEMPLATE_MO_RELEASE
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#undef RSEQ_TEMPLATE_MM_CID
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/* APIs which are not based on cpu ids. */
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#define RSEQ_TEMPLATE_CPU_ID_NONE
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#define RSEQ_TEMPLATE_MO_RELAXED
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#include "rseq-or1k-bits.h"
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#undef RSEQ_TEMPLATE_MO_RELAXED
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#undef RSEQ_TEMPLATE_CPU_ID_NONE
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