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287dcc2b0c
This adds a test for the recently added RISC-V interface for probing hardware capabilities. It happens to be the first selftest we have for RISC-V, so I've added some infrastructure for those as well. Co-developed-by: Palmer Dabbelt <palmer@rivosinc.com> Signed-off-by: Evan Green <evan@rivosinc.com> Link: https://lore.kernel.org/r/20230407231103.2622178-6-evan@rivosinc.com Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
12 lines
322 B
ArmAsm
12 lines
322 B
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (C) 2023 Rivos, Inc */
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.text
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.global riscv_hwprobe
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riscv_hwprobe:
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# Put __NR_riscv_hwprobe in the syscall number register, then just shim
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# back the kernel's return. This doesn't do any sort of errno
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# handling, the caller can deal with it.
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li a7, 258
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ecall
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ret
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