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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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2ebf31d59f
Add core KVM selftests support for LoongArch, it includes exception handler, mmu page table setup and vCPU startup entry support. Signed-off-by: Bibo Mao <maobibo@loongson.cn> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
59 lines
1.3 KiB
ArmAsm
59 lines
1.3 KiB
ArmAsm
/* SPDX-License-Identifier: GPL-2.0 */
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#include "processor.h"
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/* address of refill exception should be 4K aligned */
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.balign 4096
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.global handle_tlb_refill
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handle_tlb_refill:
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csrwr t0, LOONGARCH_CSR_TLBRSAVE
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csrrd t0, LOONGARCH_CSR_PGD
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lddir t0, t0, 3
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lddir t0, t0, 1
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ldpte t0, 0
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ldpte t0, 1
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tlbfill
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csrrd t0, LOONGARCH_CSR_TLBRSAVE
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ertn
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/*
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* save and restore all gprs except base register,
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* and default value of base register is sp ($r3).
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*/
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.macro save_gprs base
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.irp n,1,2,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
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st.d $r\n, \base, 8 * \n
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.endr
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.endm
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.macro restore_gprs base
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.irp n,1,2,4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31
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ld.d $r\n, \base, 8 * \n
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.endr
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.endm
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/* address of general exception should be 4K aligned */
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.balign 4096
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.global handle_exception
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handle_exception:
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csrwr sp, LOONGARCH_CSR_KS0
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csrrd sp, LOONGARCH_CSR_KS1
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addi.d sp, sp, -EXREGS_SIZE
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save_gprs sp
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/* save sp register to stack */
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csrrd t0, LOONGARCH_CSR_KS0
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st.d t0, sp, 3 * 8
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csrrd t0, LOONGARCH_CSR_ERA
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st.d t0, sp, PC_OFFSET_EXREGS
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csrrd t0, LOONGARCH_CSR_ESTAT
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st.d t0, sp, ESTAT_OFFSET_EXREGS
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csrrd t0, LOONGARCH_CSR_BADV
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st.d t0, sp, BADV_OFFSET_EXREGS
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or a0, sp, zero
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bl route_exception
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restore_gprs sp
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csrrd sp, LOONGARCH_CSR_KS0
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ertn
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