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7dbd26d0b2
Add coverage for FPMR to fp-ptrace. FPMR can be available independently of SVE and SME, if SME is supported then FPMR is cleared by entering and exiting streaming mode. As with other registers we generate random values to load into the register, we restrict these to bitfields which are always defined. We also leave bitfields where the valid values are affected by the set of supported FP8 formats zero to reduce complexity, it is unlikely that specific bitfields will be affected by ptrace issues. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20241112-arm64-fp-ptrace-fpmr-v2-3-250b57c61254@kernel.org [catalin.marinas@arm.com: use REG_FPMR instead of FPMR] Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
73 lines
1.1 KiB
C
73 lines
1.1 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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// Copyright (C) 2021-2 ARM Limited.
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// Original author: Mark Brown <broonie@kernel.org>
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#ifndef SME_INST_H
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#define SME_INST_H
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#define REG_FPMR S3_3_C4_C4_2
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/*
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* RDSVL X\nx, #\imm
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*/
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.macro rdsvl nx, imm
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.inst 0x4bf5800 \
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| (\imm << 5) \
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| (\nx)
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.endm
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.macro smstop
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msr S0_3_C4_C6_3, xzr
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.endm
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.macro smstart_za
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msr S0_3_C4_C5_3, xzr
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.endm
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.macro smstart_sm
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msr S0_3_C4_C3_3, xzr
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.endm
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/*
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* LDR (vector to ZA array):
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* LDR ZA[\nw, #\offset], [X\nxbase, #\offset, MUL VL]
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*/
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.macro _ldr_za nw, nxbase, offset=0
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.inst 0xe1000000 \
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| (((\nw) & 3) << 13) \
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| ((\nxbase) << 5) \
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| ((\offset) & 7)
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.endm
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/*
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* STR (vector from ZA array):
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* STR ZA[\nw, #\offset], [X\nxbase, #\offset, MUL VL]
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*/
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.macro _str_za nw, nxbase, offset=0
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.inst 0xe1200000 \
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| (((\nw) & 3) << 13) \
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| ((\nxbase) << 5) \
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| ((\offset) & 7)
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.endm
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/*
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* LDR (ZT0)
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*
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* LDR ZT0, nx
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*/
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.macro _ldr_zt nx
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.inst 0xe11f8000 \
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| (((\nx) & 0x1f) << 5)
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.endm
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/*
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* STR (ZT0)
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*
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* STR ZT0, nx
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*/
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.macro _str_zt nx
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.inst 0xe13f8000 \
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| (((\nx) & 0x1f) << 5)
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.endm
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#endif
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