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7dbd26d0b2
Add coverage for FPMR to fp-ptrace. FPMR can be available independently of SVE and SME, if SME is supported then FPMR is cleared by entering and exiting streaming mode. As with other registers we generate random values to load into the register, we restrict these to bitfields which are always defined. We also leave bitfields where the valid values are affected by the set of supported FP8 formats zero to reduce complexity, it is unlikely that specific bitfields will be affected by ptrace issues. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20241112-arm64-fp-ptrace-fpmr-v2-3-250b57c61254@kernel.org [catalin.marinas@arm.com: use REG_FPMR instead of FPMR] Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
25 lines
587 B
C
25 lines
587 B
C
// SPDX-License-Identifier: GPL-2.0-only
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// Copyright (C) 2021-3 ARM Limited.
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#ifndef FP_PTRACE_H
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#define FP_PTRACE_H
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#define SVCR_SM_SHIFT 0
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#define SVCR_ZA_SHIFT 1
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#define SVCR_SM (1 << SVCR_SM_SHIFT)
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#define SVCR_ZA (1 << SVCR_ZA_SHIFT)
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#define HAVE_SVE_SHIFT 0
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#define HAVE_SME_SHIFT 1
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#define HAVE_SME2_SHIFT 2
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#define HAVE_FA64_SHIFT 3
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#define HAVE_FPMR_SHIFT 4
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#define HAVE_SVE (1 << HAVE_SVE_SHIFT)
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#define HAVE_SME (1 << HAVE_SME_SHIFT)
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#define HAVE_SME2 (1 << HAVE_SME2_SHIFT)
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#define HAVE_FA64 (1 << HAVE_FA64_SHIFT)
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#define HAVE_FPMR (1 << HAVE_FPMR_SHIFT)
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#endif
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