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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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7dbd26d0b2
Add coverage for FPMR to fp-ptrace. FPMR can be available independently of SVE and SME, if SME is supported then FPMR is cleared by entering and exiting streaming mode. As with other registers we generate random values to load into the register, we restrict these to bitfields which are always defined. We also leave bitfields where the valid values are affected by the set of supported FP8 formats zero to reduce complexity, it is unlikely that specific bitfields will be affected by ptrace issues. Signed-off-by: Mark Brown <broonie@kernel.org> Link: https://lore.kernel.org/r/20241112-arm64-fp-ptrace-fpmr-v2-3-250b57c61254@kernel.org [catalin.marinas@arm.com: use REG_FPMR instead of FPMR] Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
292 lines
6.2 KiB
ArmAsm
292 lines
6.2 KiB
ArmAsm
// SPDX-License-Identifier: GPL-2.0-only
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// Copyright (C) 2021-3 ARM Limited.
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//
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// Assembly portion of the FP ptrace test
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//
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// Load values from memory into registers, break on a breakpoint, then
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// break on a further breakpoint
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//
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#include "fp-ptrace.h"
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#include "sme-inst.h"
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.arch_extension sve
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// Load and save register values with pauses for ptrace
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//
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// x0 - HAVE_ flags indicating which features are in use
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.globl load_and_save
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load_and_save:
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stp x11, x12, [sp, #-0x10]!
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// This should be redundant in the SVE case
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ldr x7, =v_in
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ldp q0, q1, [x7]
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ldp q2, q3, [x7, #16 * 2]
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ldp q4, q5, [x7, #16 * 4]
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ldp q6, q7, [x7, #16 * 6]
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ldp q8, q9, [x7, #16 * 8]
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ldp q10, q11, [x7, #16 * 10]
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ldp q12, q13, [x7, #16 * 12]
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ldp q14, q15, [x7, #16 * 14]
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ldp q16, q17, [x7, #16 * 16]
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ldp q18, q19, [x7, #16 * 18]
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ldp q20, q21, [x7, #16 * 20]
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ldp q22, q23, [x7, #16 * 22]
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ldp q24, q25, [x7, #16 * 24]
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ldp q26, q27, [x7, #16 * 26]
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ldp q28, q29, [x7, #16 * 28]
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ldp q30, q31, [x7, #16 * 30]
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// SME?
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tbz x0, #HAVE_SME_SHIFT, check_sve_in
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adrp x7, svcr_in
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ldr x7, [x7, :lo12:svcr_in]
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// SVCR is 0 by default, avoid triggering SME if not in use
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cbz x7, check_sve_in
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msr S3_3_C4_C2_2, x7
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// ZA?
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tbz x7, #SVCR_ZA_SHIFT, check_sm_in
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rdsvl 11, 1
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mov w12, #0
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ldr x6, =za_in
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1: _ldr_za 12, 6
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add x6, x6, x11
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add x12, x12, #1
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cmp x11, x12
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bne 1b
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// ZT?
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tbz x0, #HAVE_SME2_SHIFT, check_sm_in
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adrp x6, zt_in
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add x6, x6, :lo12:zt_in
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_ldr_zt 6
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// In streaming mode?
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check_sm_in:
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tbz x7, #SVCR_SM_SHIFT, check_sve_in
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// Load FFR if we have FA64
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ubfx x4, x0, #HAVE_FA64_SHIFT, #1
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b load_sve
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// SVE?
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check_sve_in:
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tbz x0, #HAVE_SVE_SHIFT, check_fpmr_in
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mov x4, #1
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load_sve:
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ldr x7, =z_in
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ldr z0, [x7, #0, MUL VL]
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ldr z1, [x7, #1, MUL VL]
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ldr z2, [x7, #2, MUL VL]
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ldr z3, [x7, #3, MUL VL]
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ldr z4, [x7, #4, MUL VL]
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ldr z5, [x7, #5, MUL VL]
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ldr z6, [x7, #6, MUL VL]
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ldr z7, [x7, #7, MUL VL]
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ldr z8, [x7, #8, MUL VL]
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ldr z9, [x7, #9, MUL VL]
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ldr z10, [x7, #10, MUL VL]
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ldr z11, [x7, #11, MUL VL]
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ldr z12, [x7, #12, MUL VL]
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ldr z13, [x7, #13, MUL VL]
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ldr z14, [x7, #14, MUL VL]
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ldr z15, [x7, #15, MUL VL]
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ldr z16, [x7, #16, MUL VL]
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ldr z17, [x7, #17, MUL VL]
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ldr z18, [x7, #18, MUL VL]
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ldr z19, [x7, #19, MUL VL]
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ldr z20, [x7, #20, MUL VL]
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ldr z21, [x7, #21, MUL VL]
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ldr z22, [x7, #22, MUL VL]
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ldr z23, [x7, #23, MUL VL]
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ldr z24, [x7, #24, MUL VL]
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ldr z25, [x7, #25, MUL VL]
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ldr z26, [x7, #26, MUL VL]
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ldr z27, [x7, #27, MUL VL]
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ldr z28, [x7, #28, MUL VL]
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ldr z29, [x7, #29, MUL VL]
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ldr z30, [x7, #30, MUL VL]
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ldr z31, [x7, #31, MUL VL]
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// FFR is not present in base SME
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cbz x4, 1f
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ldr x7, =ffr_in
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ldr p0, [x7]
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ldr x7, [x7, #0]
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cbz x7, 1f
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wrffr p0.b
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1:
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ldr x7, =p_in
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ldr p0, [x7, #0, MUL VL]
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ldr p1, [x7, #1, MUL VL]
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ldr p2, [x7, #2, MUL VL]
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ldr p3, [x7, #3, MUL VL]
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ldr p4, [x7, #4, MUL VL]
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ldr p5, [x7, #5, MUL VL]
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ldr p6, [x7, #6, MUL VL]
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ldr p7, [x7, #7, MUL VL]
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ldr p8, [x7, #8, MUL VL]
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ldr p9, [x7, #9, MUL VL]
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ldr p10, [x7, #10, MUL VL]
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ldr p11, [x7, #11, MUL VL]
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ldr p12, [x7, #12, MUL VL]
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ldr p13, [x7, #13, MUL VL]
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ldr p14, [x7, #14, MUL VL]
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ldr p15, [x7, #15, MUL VL]
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// This has to come after we set PSTATE.SM
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check_fpmr_in:
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tbz x0, #HAVE_FPMR_SHIFT, wait_for_writes
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adrp x7, fpmr_in
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ldr x7, [x7, :lo12:fpmr_in]
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msr REG_FPMR, x7
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wait_for_writes:
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// Wait for the parent
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brk #0
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// Save values
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ldr x7, =v_out
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stp q0, q1, [x7]
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stp q2, q3, [x7, #16 * 2]
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stp q4, q5, [x7, #16 * 4]
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stp q6, q7, [x7, #16 * 6]
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stp q8, q9, [x7, #16 * 8]
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stp q10, q11, [x7, #16 * 10]
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stp q12, q13, [x7, #16 * 12]
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stp q14, q15, [x7, #16 * 14]
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stp q16, q17, [x7, #16 * 16]
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stp q18, q19, [x7, #16 * 18]
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stp q20, q21, [x7, #16 * 20]
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stp q22, q23, [x7, #16 * 22]
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stp q24, q25, [x7, #16 * 24]
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stp q26, q27, [x7, #16 * 26]
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stp q28, q29, [x7, #16 * 28]
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stp q30, q31, [x7, #16 * 30]
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tbz x0, #HAVE_FPMR_SHIFT, check_sme_out
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mrs x7, REG_FPMR
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adrp x6, fpmr_out
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str x7, [x6, :lo12:fpmr_out]
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check_sme_out:
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tbz x0, #HAVE_SME_SHIFT, check_sve_out
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rdsvl 11, 1
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adrp x6, sme_vl_out
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str x11, [x6, :lo12:sme_vl_out]
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mrs x7, S3_3_C4_C2_2
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adrp x6, svcr_out
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str x7, [x6, :lo12:svcr_out]
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// ZA?
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tbz x7, #SVCR_ZA_SHIFT, check_sm_out
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mov w12, #0
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ldr x6, =za_out
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1: _str_za 12, 6
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add x6, x6, x11
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add x12, x12, #1
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cmp x11, x12
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bne 1b
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// ZT?
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tbz x0, #HAVE_SME2_SHIFT, check_sm_out
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adrp x6, zt_out
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add x6, x6, :lo12:zt_out
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_str_zt 6
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// In streaming mode?
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check_sm_out:
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tbz x7, #SVCR_SM_SHIFT, check_sve_out
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// Do we have FA64 and FFR?
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ubfx x4, x0, #HAVE_FA64_SHIFT, #1
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b read_sve
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// SVE?
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check_sve_out:
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tbz x0, #HAVE_SVE_SHIFT, wait_for_reads
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mov x4, #1
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rdvl x7, #1
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adrp x6, sve_vl_out
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str x7, [x6, :lo12:sve_vl_out]
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read_sve:
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ldr x7, =z_out
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str z0, [x7, #0, MUL VL]
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str z1, [x7, #1, MUL VL]
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str z2, [x7, #2, MUL VL]
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str z3, [x7, #3, MUL VL]
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str z4, [x7, #4, MUL VL]
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str z5, [x7, #5, MUL VL]
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str z6, [x7, #6, MUL VL]
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str z7, [x7, #7, MUL VL]
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str z8, [x7, #8, MUL VL]
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str z9, [x7, #9, MUL VL]
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str z10, [x7, #10, MUL VL]
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str z11, [x7, #11, MUL VL]
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str z12, [x7, #12, MUL VL]
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str z13, [x7, #13, MUL VL]
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str z14, [x7, #14, MUL VL]
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str z15, [x7, #15, MUL VL]
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str z16, [x7, #16, MUL VL]
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str z17, [x7, #17, MUL VL]
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str z18, [x7, #18, MUL VL]
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str z19, [x7, #19, MUL VL]
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str z20, [x7, #20, MUL VL]
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str z21, [x7, #21, MUL VL]
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str z22, [x7, #22, MUL VL]
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str z23, [x7, #23, MUL VL]
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str z24, [x7, #24, MUL VL]
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str z25, [x7, #25, MUL VL]
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str z26, [x7, #26, MUL VL]
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str z27, [x7, #27, MUL VL]
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str z28, [x7, #28, MUL VL]
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str z29, [x7, #29, MUL VL]
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str z30, [x7, #30, MUL VL]
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str z31, [x7, #31, MUL VL]
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ldr x7, =p_out
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str p0, [x7, #0, MUL VL]
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str p1, [x7, #1, MUL VL]
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str p2, [x7, #2, MUL VL]
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str p3, [x7, #3, MUL VL]
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str p4, [x7, #4, MUL VL]
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str p5, [x7, #5, MUL VL]
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str p6, [x7, #6, MUL VL]
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str p7, [x7, #7, MUL VL]
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str p8, [x7, #8, MUL VL]
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str p9, [x7, #9, MUL VL]
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str p10, [x7, #10, MUL VL]
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str p11, [x7, #11, MUL VL]
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str p12, [x7, #12, MUL VL]
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str p13, [x7, #13, MUL VL]
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str p14, [x7, #14, MUL VL]
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str p15, [x7, #15, MUL VL]
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// Only save FFR if it exists
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cbz x4, wait_for_reads
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ldr x7, =ffr_out
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rdffr p0.b
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str p0, [x7]
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wait_for_reads:
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// Wait for the parent
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brk #0
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// Ensure we don't leave ourselves in streaming mode
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tbz x0, #HAVE_SME_SHIFT, out
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msr S3_3_C4_C2_2, xzr
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out:
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ldp x11, x12, [sp, #-0x10]
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ret
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