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fd509c6f8e
Add Tegra264 AMX support with following changes: - Add soc_data for Tegra264-specific variations - Tegra264 AMX supports 32 output channels, hence update the capture DAI channels_max parameter and CIF configuration API. - Register offsets and default values are updated to align with Tegra264. - Add 128 byte map controls for Tegra264 to accommodate each byte per channel (32channels x 32bits). Signed-off-by: Sheetal <sheetal@nvidia.com> Link: https://patch.msgid.link/20250512051747.1026770-9-sheetal@nvidia.com Signed-off-by: Mark Brown <broonie@kernel.org>
113 lines
3.7 KiB
C
113 lines
3.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only
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* SPDX-FileCopyrightText: Copyright (c) 2021-2025 NVIDIA CORPORATION. All rights reserved.
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*
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* tegra210_amx.h - Definitions for Tegra210 AMX driver
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*
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*/
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#ifndef __TEGRA210_AMX_H__
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#define __TEGRA210_AMX_H__
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/* Register offsets from TEGRA210_AMX*_BASE */
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#define TEGRA210_AMX_RX_STATUS 0x0c
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#define TEGRA210_AMX_RX_INT_STATUS 0x10
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#define TEGRA210_AMX_RX_INT_MASK 0x14
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#define TEGRA210_AMX_RX_INT_SET 0x18
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#define TEGRA210_AMX_RX_INT_CLEAR 0x1c
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#define TEGRA210_AMX_RX1_CIF_CTRL 0x20
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#define TEGRA210_AMX_RX2_CIF_CTRL 0x24
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#define TEGRA210_AMX_RX3_CIF_CTRL 0x28
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#define TEGRA210_AMX_RX4_CIF_CTRL 0x2c
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#define TEGRA210_AMX_TX_STATUS 0x4c
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#define TEGRA210_AMX_TX_INT_STATUS 0x50
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#define TEGRA210_AMX_TX_INT_MASK 0x54
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#define TEGRA210_AMX_TX_INT_SET 0x58
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#define TEGRA210_AMX_TX_INT_CLEAR 0x5c
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#define TEGRA210_AMX_TX_CIF_CTRL 0x60
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#define TEGRA210_AMX_ENABLE 0x80
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#define TEGRA210_AMX_SOFT_RESET 0x84
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#define TEGRA210_AMX_CG 0x88
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#define TEGRA210_AMX_STATUS 0x8c
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#define TEGRA210_AMX_INT_STATUS 0x90
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#define TEGRA210_AMX_CTRL 0xa4
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#define TEGRA210_AMX_OUT_BYTE_EN0 0xa8
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#define TEGRA210_AMX_CYA 0xb0
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#define TEGRA210_AMX_CFG_RAM_CTRL 0xb8
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#define TEGRA210_AMX_CFG_RAM_DATA 0xbc
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#define TEGRA194_AMX_RX1_FRAME_PERIOD 0xc0
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#define TEGRA194_AMX_RX4_FRAME_PERIOD 0xcc
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#define TEGRA194_AMX_RX4_LAST_FRAME_PERIOD 0xdc
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#define TEGRA264_AMX_STREAMS_AUTO_DISABLE 0xb8
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#define TEGRA264_AMX_CFG_RAM_CTRL 0xc0
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#define TEGRA264_AMX_CFG_RAM_DATA 0xc4
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#define TEGRA264_AMX_RX1_FRAME_PERIOD 0xc8
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#define TEGRA264_AMX_RX4_FRAME_PERIOD 0xd4
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#define TEGRA264_AMX_RX4_LAST_FRAME_PERIOD 0xe4
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/* Fields in TEGRA210_AMX_ENABLE */
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#define TEGRA210_AMX_ENABLE_SHIFT 0
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/* Fields in TEGRA210_AMX_CTRL */
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#define TEGRA210_AMX_CTRL_MSTR_RX_NUM_SHIFT 14
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#define TEGRA210_AMX_CTRL_MSTR_RX_NUM_MASK (3 << TEGRA210_AMX_CTRL_MSTR_RX_NUM_SHIFT)
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#define TEGRA210_AMX_CTRL_RX_DEP_SHIFT 12
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#define TEGRA210_AMX_CTRL_RX_DEP_MASK (3 << TEGRA210_AMX_CTRL_RX_DEP_SHIFT)
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/* Fields in TEGRA210_AMX_CFG_RAM_CTRL */
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#define TEGRA210_AMX_CFG_RAM_CTRL_RW_SHIFT 14
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#define TEGRA210_AMX_CFG_RAM_CTRL_RW_WRITE (1 << TEGRA210_AMX_CFG_RAM_CTRL_RW_SHIFT)
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#define TEGRA210_AMX_CFG_RAM_CTRL_ADDR_INIT_EN_SHIFT 13
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#define TEGRA210_AMX_CFG_RAM_CTRL_ADDR_INIT_EN (1 << TEGRA210_AMX_CFG_RAM_CTRL_ADDR_INIT_EN_SHIFT)
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#define TEGRA210_AMX_CFG_RAM_CTRL_SEQ_ACCESS_EN_SHIFT 12
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#define TEGRA210_AMX_CFG_RAM_CTRL_SEQ_ACCESS_EN (1 << TEGRA210_AMX_CFG_RAM_CTRL_SEQ_ACCESS_EN_SHIFT)
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#define TEGRA210_AMX_CFG_CTRL_RAM_ADDR_SHIFT 0
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/* Fields in TEGRA210_AMX_SOFT_RESET */
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#define TEGRA210_AMX_SOFT_RESET_SOFT_EN 1
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#define TEGRA210_AMX_SOFT_RESET_SOFT_RESET_MASK TEGRA210_AMX_SOFT_RESET_SOFT_EN
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#define TEGRA210_AMX_AUDIOCIF_CH_STRIDE 4
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#define TEGRA210_AMX_RAM_DEPTH 16
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#define TEGRA210_AMX_MAP_STREAM_NUM_SHIFT 6
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#define TEGRA210_AMX_MAP_WORD_NUM_SHIFT 2
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#define TEGRA210_AMX_MAP_BYTE_NUM_SHIFT 0
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#define TEGRA210_AMX_BYTE_MASK_COUNT 2
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#define TEGRA210_AMX_MAX_CHANNEL 16
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#define TEGRA210_AMX_AUTO_DISABLE_OFFSET 0
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#define TEGRA264_AMX_RAM_DEPTH 32
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#define TEGRA264_AMX_BYTE_MASK_COUNT 4
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#define TEGRA264_AMX_MAX_CHANNEL 32
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#define TEGRA264_AMX_AUTO_DISABLE_OFFSET 8
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#define TEGRA_AMX_OUT_DAI_ID 4
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enum {
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TEGRA210_AMX_WAIT_ON_ALL,
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TEGRA210_AMX_WAIT_ON_ANY,
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};
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struct tegra210_amx_soc_data {
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const struct regmap_config *regmap_conf;
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bool auto_disable;
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const struct snd_kcontrol_new *controls;
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unsigned int num_controls;
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unsigned int max_ch;
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unsigned int ram_depth;
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unsigned int byte_mask_size;
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unsigned int reg_offset;
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};
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struct tegra210_amx {
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const struct tegra210_amx_soc_data *soc_data;
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unsigned int *map;
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unsigned int *byte_mask;
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struct regmap *regmap;
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};
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#endif
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