mirror of
git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
synced 2025-08-05 16:54:27 +00:00
7668c6378b
Add Tegra264 I2S support with following changes: - Add soc_data for Tegra264-specific variations - Tegra264 supports 32 RX and 32 TX ADMAIF channels and each ADMAIF stream supports max 32 channels. To accommodate the change dais, CIF configuration API and driver components are updated. - Register offsets and default values are updated to align with Tegra264. Signed-off-by: Sheetal <sheetal@nvidia.com> Link: https://patch.msgid.link/20250512051747.1026770-5-sheetal@nvidia.com Signed-off-by: Mark Brown <broonie@kernel.org>
241 lines
11 KiB
C
241 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0-only
|
|
* SPDX-FileCopyrightText: Copyright (c) 2020-2025 NVIDIA CORPORATION & AFFILIATES.
|
|
* All rights reserved.
|
|
*
|
|
* tegra210_admaif.h - Tegra ADMAIF registers
|
|
*
|
|
*/
|
|
|
|
#ifndef __TEGRA_ADMAIF_H__
|
|
#define __TEGRA_ADMAIF_H__
|
|
|
|
#define TEGRA_ADMAIF_CHANNEL_REG_STRIDE 0x40
|
|
/* Tegra210 specific */
|
|
#define TEGRA210_ADMAIF_LAST_REG 0x75f
|
|
#define TEGRA210_ADMAIF_CHANNEL_COUNT 10
|
|
#define TEGRA210_ADMAIF_RX_BASE 0x0
|
|
#define TEGRA210_ADMAIF_TX_BASE 0x300
|
|
#define TEGRA210_ADMAIF_GLOBAL_BASE 0x700
|
|
#define TEGRA210_ADMAIF_MAX_CHANNEL 16
|
|
/* Tegra186 specific */
|
|
#define TEGRA186_ADMAIF_LAST_REG 0xd5f
|
|
#define TEGRA186_ADMAIF_CHANNEL_COUNT 20
|
|
#define TEGRA186_ADMAIF_RX_BASE 0x0
|
|
#define TEGRA186_ADMAIF_TX_BASE 0x500
|
|
#define TEGRA186_ADMAIF_GLOBAL_BASE 0xd00
|
|
#define TEGRA186_ADMAIF_MAX_CHANNEL 16
|
|
/* Tegra264 specific */
|
|
#define TEGRA264_ADMAIF_LAST_REG 0x205f
|
|
#define TEGRA264_ADMAIF_CHANNEL_COUNT 32
|
|
#define TEGRA264_ADMAIF_RX_BASE 0x0
|
|
#define TEGRA264_ADMAIF_TX_BASE 0x1000
|
|
#define TEGRA264_ADMAIF_GLOBAL_BASE 0x2000
|
|
#define TEGRA264_ADMAIF_MAX_CHANNEL 32
|
|
/* Global registers */
|
|
#define TEGRA_ADMAIF_GLOBAL_ENABLE 0x0
|
|
#define TEGRA_ADMAIF_GLOBAL_CG_0 0x8
|
|
#define TEGRA_ADMAIF_GLOBAL_STATUS 0x10
|
|
#define TEGRA_ADMAIF_GLOBAL_RX_ENABLE_STATUS 0x20
|
|
#define TEGRA_ADMAIF_GLOBAL_TX_ENABLE_STATUS 0x24
|
|
/* RX channel registers */
|
|
#define TEGRA_ADMAIF_RX_ENABLE 0x0
|
|
#define TEGRA_ADMAIF_RX_SOFT_RESET 0x4
|
|
#define TEGRA_ADMAIF_RX_STATUS 0xc
|
|
#define TEGRA_ADMAIF_RX_INT_STATUS 0x10
|
|
#define TEGRA_ADMAIF_RX_INT_MASK 0x14
|
|
#define TEGRA_ADMAIF_RX_INT_SET 0x18
|
|
#define TEGRA_ADMAIF_RX_INT_CLEAR 0x1c
|
|
#define TEGRA_ADMAIF_CH_ACIF_RX_CTRL 0x20
|
|
#define TEGRA_ADMAIF_RX_FIFO_CTRL 0x28
|
|
#define TEGRA_ADMAIF_RX_FIFO_READ 0x2c
|
|
/* TX channel registers */
|
|
#define TEGRA_ADMAIF_TX_ENABLE 0x0
|
|
#define TEGRA_ADMAIF_TX_SOFT_RESET 0x4
|
|
#define TEGRA_ADMAIF_TX_STATUS 0xc
|
|
#define TEGRA_ADMAIF_TX_INT_STATUS 0x10
|
|
#define TEGRA_ADMAIF_TX_INT_MASK 0x14
|
|
#define TEGRA_ADMAIF_TX_INT_SET 0x18
|
|
#define TEGRA_ADMAIF_TX_INT_CLEAR 0x1c
|
|
#define TEGRA_ADMAIF_CH_ACIF_TX_CTRL 0x20
|
|
#define TEGRA_ADMAIF_TX_FIFO_CTRL 0x28
|
|
#define TEGRA_ADMAIF_TX_FIFO_WRITE 0x2c
|
|
/* Bit fields */
|
|
#define PACK8_EN_SHIFT 31
|
|
#define PACK8_EN_MASK BIT(PACK8_EN_SHIFT)
|
|
#define PACK8_EN BIT(PACK8_EN_SHIFT)
|
|
#define PACK16_EN_SHIFT 30
|
|
#define PACK16_EN_MASK BIT(PACK16_EN_SHIFT)
|
|
#define PACK16_EN BIT(PACK16_EN_SHIFT)
|
|
#define TX_ENABLE_SHIFT 0
|
|
#define TX_ENABLE_MASK BIT(TX_ENABLE_SHIFT)
|
|
#define TX_ENABLE BIT(TX_ENABLE_SHIFT)
|
|
#define RX_ENABLE_SHIFT 0
|
|
#define RX_ENABLE_MASK BIT(RX_ENABLE_SHIFT)
|
|
#define RX_ENABLE BIT(RX_ENABLE_SHIFT)
|
|
#define SW_RESET_MASK 1
|
|
#define SW_RESET 1
|
|
/* Default values - Tegra210 */
|
|
#define TEGRA210_ADMAIF_CIF_REG_DEFAULT 0x00007700
|
|
#define TEGRA210_ADMAIF_RX1_FIFO_CTRL_REG_DEFAULT 0x00000300
|
|
#define TEGRA210_ADMAIF_RX2_FIFO_CTRL_REG_DEFAULT 0x00000304
|
|
#define TEGRA210_ADMAIF_RX3_FIFO_CTRL_REG_DEFAULT 0x00000208
|
|
#define TEGRA210_ADMAIF_RX4_FIFO_CTRL_REG_DEFAULT 0x0000020b
|
|
#define TEGRA210_ADMAIF_RX5_FIFO_CTRL_REG_DEFAULT 0x0000020e
|
|
#define TEGRA210_ADMAIF_RX6_FIFO_CTRL_REG_DEFAULT 0x00000211
|
|
#define TEGRA210_ADMAIF_RX7_FIFO_CTRL_REG_DEFAULT 0x00000214
|
|
#define TEGRA210_ADMAIF_RX8_FIFO_CTRL_REG_DEFAULT 0x00000217
|
|
#define TEGRA210_ADMAIF_RX9_FIFO_CTRL_REG_DEFAULT 0x0000021a
|
|
#define TEGRA210_ADMAIF_RX10_FIFO_CTRL_REG_DEFAULT 0x0000021d
|
|
#define TEGRA210_ADMAIF_TX1_FIFO_CTRL_REG_DEFAULT 0x02000300
|
|
#define TEGRA210_ADMAIF_TX2_FIFO_CTRL_REG_DEFAULT 0x02000304
|
|
#define TEGRA210_ADMAIF_TX3_FIFO_CTRL_REG_DEFAULT 0x01800208
|
|
#define TEGRA210_ADMAIF_TX4_FIFO_CTRL_REG_DEFAULT 0x0180020b
|
|
#define TEGRA210_ADMAIF_TX5_FIFO_CTRL_REG_DEFAULT 0x0180020e
|
|
#define TEGRA210_ADMAIF_TX6_FIFO_CTRL_REG_DEFAULT 0x01800211
|
|
#define TEGRA210_ADMAIF_TX7_FIFO_CTRL_REG_DEFAULT 0x01800214
|
|
#define TEGRA210_ADMAIF_TX8_FIFO_CTRL_REG_DEFAULT 0x01800217
|
|
#define TEGRA210_ADMAIF_TX9_FIFO_CTRL_REG_DEFAULT 0x0180021a
|
|
#define TEGRA210_ADMAIF_TX10_FIFO_CTRL_REG_DEFAULT 0x0180021d
|
|
/* Default values - Tegra186 */
|
|
#define TEGRA186_ADMAIF_CIF_REG_DEFAULT 0x00007700
|
|
#define TEGRA186_ADMAIF_RX1_FIFO_CTRL_REG_DEFAULT 0x00000300
|
|
#define TEGRA186_ADMAIF_RX2_FIFO_CTRL_REG_DEFAULT 0x00000304
|
|
#define TEGRA186_ADMAIF_RX3_FIFO_CTRL_REG_DEFAULT 0x00000308
|
|
#define TEGRA186_ADMAIF_RX4_FIFO_CTRL_REG_DEFAULT 0x0000030c
|
|
#define TEGRA186_ADMAIF_RX5_FIFO_CTRL_REG_DEFAULT 0x00000210
|
|
#define TEGRA186_ADMAIF_RX6_FIFO_CTRL_REG_DEFAULT 0x00000213
|
|
#define TEGRA186_ADMAIF_RX7_FIFO_CTRL_REG_DEFAULT 0x00000216
|
|
#define TEGRA186_ADMAIF_RX8_FIFO_CTRL_REG_DEFAULT 0x00000219
|
|
#define TEGRA186_ADMAIF_RX9_FIFO_CTRL_REG_DEFAULT 0x0000021c
|
|
#define TEGRA186_ADMAIF_RX10_FIFO_CTRL_REG_DEFAULT 0x0000021f
|
|
#define TEGRA186_ADMAIF_RX11_FIFO_CTRL_REG_DEFAULT 0x00000222
|
|
#define TEGRA186_ADMAIF_RX12_FIFO_CTRL_REG_DEFAULT 0x00000225
|
|
#define TEGRA186_ADMAIF_RX13_FIFO_CTRL_REG_DEFAULT 0x00000228
|
|
#define TEGRA186_ADMAIF_RX14_FIFO_CTRL_REG_DEFAULT 0x0000022b
|
|
#define TEGRA186_ADMAIF_RX15_FIFO_CTRL_REG_DEFAULT 0x0000022e
|
|
#define TEGRA186_ADMAIF_RX16_FIFO_CTRL_REG_DEFAULT 0x00000231
|
|
#define TEGRA186_ADMAIF_RX17_FIFO_CTRL_REG_DEFAULT 0x00000234
|
|
#define TEGRA186_ADMAIF_RX18_FIFO_CTRL_REG_DEFAULT 0x00000237
|
|
#define TEGRA186_ADMAIF_RX19_FIFO_CTRL_REG_DEFAULT 0x0000023a
|
|
#define TEGRA186_ADMAIF_RX20_FIFO_CTRL_REG_DEFAULT 0x0000023d
|
|
#define TEGRA186_ADMAIF_TX1_FIFO_CTRL_REG_DEFAULT 0x02000300
|
|
#define TEGRA186_ADMAIF_TX2_FIFO_CTRL_REG_DEFAULT 0x02000304
|
|
#define TEGRA186_ADMAIF_TX3_FIFO_CTRL_REG_DEFAULT 0x02000308
|
|
#define TEGRA186_ADMAIF_TX4_FIFO_CTRL_REG_DEFAULT 0x0200030c
|
|
#define TEGRA186_ADMAIF_TX5_FIFO_CTRL_REG_DEFAULT 0x01800210
|
|
#define TEGRA186_ADMAIF_TX6_FIFO_CTRL_REG_DEFAULT 0x01800213
|
|
#define TEGRA186_ADMAIF_TX7_FIFO_CTRL_REG_DEFAULT 0x01800216
|
|
#define TEGRA186_ADMAIF_TX8_FIFO_CTRL_REG_DEFAULT 0x01800219
|
|
#define TEGRA186_ADMAIF_TX9_FIFO_CTRL_REG_DEFAULT 0x0180021c
|
|
#define TEGRA186_ADMAIF_TX10_FIFO_CTRL_REG_DEFAULT 0x0180021f
|
|
#define TEGRA186_ADMAIF_TX11_FIFO_CTRL_REG_DEFAULT 0x01800222
|
|
#define TEGRA186_ADMAIF_TX12_FIFO_CTRL_REG_DEFAULT 0x01800225
|
|
#define TEGRA186_ADMAIF_TX13_FIFO_CTRL_REG_DEFAULT 0x01800228
|
|
#define TEGRA186_ADMAIF_TX14_FIFO_CTRL_REG_DEFAULT 0x0180022b
|
|
#define TEGRA186_ADMAIF_TX15_FIFO_CTRL_REG_DEFAULT 0x0180022e
|
|
#define TEGRA186_ADMAIF_TX16_FIFO_CTRL_REG_DEFAULT 0x01800231
|
|
#define TEGRA186_ADMAIF_TX17_FIFO_CTRL_REG_DEFAULT 0x01800234
|
|
#define TEGRA186_ADMAIF_TX18_FIFO_CTRL_REG_DEFAULT 0x01800237
|
|
#define TEGRA186_ADMAIF_TX19_FIFO_CTRL_REG_DEFAULT 0x0180023a
|
|
#define TEGRA186_ADMAIF_TX20_FIFO_CTRL_REG_DEFAULT 0x0180023d
|
|
/* Default values - Tegra264 */
|
|
#define TEGRA264_ADMAIF_CIF_REG_DEFAULT 0x00003f00
|
|
#define TEGRA264_ADMAIF_RX1_FIFO_CTRL_REG_DEFAULT 0x00000200
|
|
#define TEGRA264_ADMAIF_RX2_FIFO_CTRL_REG_DEFAULT 0x00000203
|
|
#define TEGRA264_ADMAIF_RX3_FIFO_CTRL_REG_DEFAULT 0x00000206
|
|
#define TEGRA264_ADMAIF_RX4_FIFO_CTRL_REG_DEFAULT 0x00000209
|
|
#define TEGRA264_ADMAIF_RX5_FIFO_CTRL_REG_DEFAULT 0x0000020c
|
|
#define TEGRA264_ADMAIF_RX6_FIFO_CTRL_REG_DEFAULT 0x0000020f
|
|
#define TEGRA264_ADMAIF_RX7_FIFO_CTRL_REG_DEFAULT 0x00000212
|
|
#define TEGRA264_ADMAIF_RX8_FIFO_CTRL_REG_DEFAULT 0x00000215
|
|
#define TEGRA264_ADMAIF_RX9_FIFO_CTRL_REG_DEFAULT 0x00000218
|
|
#define TEGRA264_ADMAIF_RX10_FIFO_CTRL_REG_DEFAULT 0x0000021b
|
|
#define TEGRA264_ADMAIF_RX11_FIFO_CTRL_REG_DEFAULT 0x0000021e
|
|
#define TEGRA264_ADMAIF_RX12_FIFO_CTRL_REG_DEFAULT 0x00000221
|
|
#define TEGRA264_ADMAIF_RX13_FIFO_CTRL_REG_DEFAULT 0x00000224
|
|
#define TEGRA264_ADMAIF_RX14_FIFO_CTRL_REG_DEFAULT 0x00000227
|
|
#define TEGRA264_ADMAIF_RX15_FIFO_CTRL_REG_DEFAULT 0x0000022a
|
|
#define TEGRA264_ADMAIF_RX16_FIFO_CTRL_REG_DEFAULT 0x0000022d
|
|
#define TEGRA264_ADMAIF_RX17_FIFO_CTRL_REG_DEFAULT 0x00000230
|
|
#define TEGRA264_ADMAIF_RX18_FIFO_CTRL_REG_DEFAULT 0x00000233
|
|
#define TEGRA264_ADMAIF_RX19_FIFO_CTRL_REG_DEFAULT 0x00000236
|
|
#define TEGRA264_ADMAIF_RX20_FIFO_CTRL_REG_DEFAULT 0x00000239
|
|
#define TEGRA264_ADMAIF_RX21_FIFO_CTRL_REG_DEFAULT 0x0000023c
|
|
#define TEGRA264_ADMAIF_RX22_FIFO_CTRL_REG_DEFAULT 0x0000023f
|
|
#define TEGRA264_ADMAIF_RX23_FIFO_CTRL_REG_DEFAULT 0x00000242
|
|
#define TEGRA264_ADMAIF_RX24_FIFO_CTRL_REG_DEFAULT 0x00000245
|
|
#define TEGRA264_ADMAIF_RX25_FIFO_CTRL_REG_DEFAULT 0x00000248
|
|
#define TEGRA264_ADMAIF_RX26_FIFO_CTRL_REG_DEFAULT 0x0000024b
|
|
#define TEGRA264_ADMAIF_RX27_FIFO_CTRL_REG_DEFAULT 0x0000024e
|
|
#define TEGRA264_ADMAIF_RX28_FIFO_CTRL_REG_DEFAULT 0x00000251
|
|
#define TEGRA264_ADMAIF_RX29_FIFO_CTRL_REG_DEFAULT 0x00000254
|
|
#define TEGRA264_ADMAIF_RX30_FIFO_CTRL_REG_DEFAULT 0x00000257
|
|
#define TEGRA264_ADMAIF_RX31_FIFO_CTRL_REG_DEFAULT 0x0000025a
|
|
#define TEGRA264_ADMAIF_RX32_FIFO_CTRL_REG_DEFAULT 0x0000025d
|
|
#define TEGRA264_ADMAIF_TX1_FIFO_CTRL_REG_DEFAULT 0x01800200
|
|
#define TEGRA264_ADMAIF_TX2_FIFO_CTRL_REG_DEFAULT 0x01800203
|
|
#define TEGRA264_ADMAIF_TX3_FIFO_CTRL_REG_DEFAULT 0x01800206
|
|
#define TEGRA264_ADMAIF_TX4_FIFO_CTRL_REG_DEFAULT 0x01800209
|
|
#define TEGRA264_ADMAIF_TX5_FIFO_CTRL_REG_DEFAULT 0x0180020c
|
|
#define TEGRA264_ADMAIF_TX6_FIFO_CTRL_REG_DEFAULT 0x0180020f
|
|
#define TEGRA264_ADMAIF_TX7_FIFO_CTRL_REG_DEFAULT 0x01800212
|
|
#define TEGRA264_ADMAIF_TX8_FIFO_CTRL_REG_DEFAULT 0x01800215
|
|
#define TEGRA264_ADMAIF_TX9_FIFO_CTRL_REG_DEFAULT 0x01800218
|
|
#define TEGRA264_ADMAIF_TX10_FIFO_CTRL_REG_DEFAULT 0x0180021b
|
|
#define TEGRA264_ADMAIF_TX11_FIFO_CTRL_REG_DEFAULT 0x0180021e
|
|
#define TEGRA264_ADMAIF_TX12_FIFO_CTRL_REG_DEFAULT 0x01800221
|
|
#define TEGRA264_ADMAIF_TX13_FIFO_CTRL_REG_DEFAULT 0x01800224
|
|
#define TEGRA264_ADMAIF_TX14_FIFO_CTRL_REG_DEFAULT 0x01800227
|
|
#define TEGRA264_ADMAIF_TX15_FIFO_CTRL_REG_DEFAULT 0x0180022a
|
|
#define TEGRA264_ADMAIF_TX16_FIFO_CTRL_REG_DEFAULT 0x0180022d
|
|
#define TEGRA264_ADMAIF_TX17_FIFO_CTRL_REG_DEFAULT 0x01800230
|
|
#define TEGRA264_ADMAIF_TX18_FIFO_CTRL_REG_DEFAULT 0x01800233
|
|
#define TEGRA264_ADMAIF_TX19_FIFO_CTRL_REG_DEFAULT 0x01800236
|
|
#define TEGRA264_ADMAIF_TX20_FIFO_CTRL_REG_DEFAULT 0x01800239
|
|
#define TEGRA264_ADMAIF_TX21_FIFO_CTRL_REG_DEFAULT 0x0180023c
|
|
#define TEGRA264_ADMAIF_TX22_FIFO_CTRL_REG_DEFAULT 0x0180023f
|
|
#define TEGRA264_ADMAIF_TX23_FIFO_CTRL_REG_DEFAULT 0x01800242
|
|
#define TEGRA264_ADMAIF_TX24_FIFO_CTRL_REG_DEFAULT 0x01800245
|
|
#define TEGRA264_ADMAIF_TX25_FIFO_CTRL_REG_DEFAULT 0x01800248
|
|
#define TEGRA264_ADMAIF_TX26_FIFO_CTRL_REG_DEFAULT 0x0180024b
|
|
#define TEGRA264_ADMAIF_TX27_FIFO_CTRL_REG_DEFAULT 0x0180024e
|
|
#define TEGRA264_ADMAIF_TX28_FIFO_CTRL_REG_DEFAULT 0x01800251
|
|
#define TEGRA264_ADMAIF_TX29_FIFO_CTRL_REG_DEFAULT 0x01800254
|
|
#define TEGRA264_ADMAIF_TX30_FIFO_CTRL_REG_DEFAULT 0x01800257
|
|
#define TEGRA264_ADMAIF_TX31_FIFO_CTRL_REG_DEFAULT 0x0180025a
|
|
#define TEGRA264_ADMAIF_TX32_FIFO_CTRL_REG_DEFAULT 0x0180025d
|
|
|
|
enum {
|
|
DATA_8BIT,
|
|
DATA_16BIT,
|
|
DATA_32BIT
|
|
};
|
|
|
|
enum {
|
|
ADMAIF_RX_PATH,
|
|
ADMAIF_TX_PATH,
|
|
ADMAIF_PATHS,
|
|
};
|
|
|
|
struct tegra_admaif_soc_data {
|
|
const struct snd_soc_component_driver *cmpnt;
|
|
const struct regmap_config *regmap_conf;
|
|
struct snd_soc_dai_driver *dais;
|
|
unsigned int global_base;
|
|
unsigned int tx_base;
|
|
unsigned int rx_base;
|
|
unsigned int num_ch;
|
|
unsigned int max_stream_ch;
|
|
};
|
|
|
|
struct tegra_admaif {
|
|
struct snd_dmaengine_dai_dma_data *capture_dma_data;
|
|
struct snd_dmaengine_dai_dma_data *playback_dma_data;
|
|
const struct tegra_admaif_soc_data *soc_data;
|
|
unsigned int *mono_to_stereo[ADMAIF_PATHS];
|
|
unsigned int *stereo_to_mono[ADMAIF_PATHS];
|
|
struct regmap *regmap;
|
|
struct tegra_adma_isomgr *adma_isomgr;
|
|
};
|
|
|
|
#endif
|