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820bcaeb1f
Platforms like i.MX93/91 only have one audio PLL. Some sample rates are not supported. Add common function to constrain rates according to different clock sources. Signed-off-by: Chancel Liu <chancel.liu@nxp.com> Link: https://patch.msgid.link/20241126115440.3929061-2-chancel.liu@nxp.com Acked-by: Shengjiu Wang <shengjiu.wang@gmail.com> Signed-off-by: Mark Brown <broonie@kernel.org>
34 lines
1,018 B
C
34 lines
1,018 B
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Freescale ALSA SoC Machine driver utility
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*
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* Author: Timur Tabi <timur@freescale.com>
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*
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* Copyright 2010 Freescale Semiconductor, Inc.
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*/
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#ifndef _FSL_UTILS_H
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#define _FSL_UTILS_H
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#define DAI_NAME_SIZE 32
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struct snd_soc_dai_link;
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struct device_node;
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int fsl_asoc_get_dma_channel(struct device_node *ssi_np, const char *name,
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struct snd_soc_dai_link *dai,
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unsigned int *dma_channel_id,
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unsigned int *dma_id);
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void fsl_asoc_get_pll_clocks(struct device *dev, struct clk **pll8k_clk,
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struct clk **pll11k_clk);
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void fsl_asoc_reparent_pll_clocks(struct device *dev, struct clk *clk,
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struct clk *pll8k_clk,
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struct clk *pll11k_clk, u64 ratio);
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void fsl_asoc_constrain_rates(struct snd_pcm_hw_constraint_list *target_constr,
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const struct snd_pcm_hw_constraint_list *original_constr,
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struct clk *pll8k_clk, struct clk *pll11k_clk,
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struct clk *ext_clk, int *target_rates);
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#endif /* _FSL_UTILS_H */
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