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git://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git
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da4fd65773
Move the mips-optimized CRC code from arch/mips/lib/crc* into its new location in lib/crc/mips/, and wire it up in the new way. This new way of organizing the CRC code eliminates the need to artificially split the code for each CRC variant into separate arch and generic modules, enabling better inlining and dead code elimination. For more details, see "lib/crc: Prepare for arch-optimized code in subdirs of lib/crc/". Reviewed-by: "Martin K. Petersen" <martin.petersen@oracle.com> Acked-by: Ingo Molnar <mingo@kernel.org> Acked-by: "Jason A. Donenfeld" <Jason@zx2c4.com> Link: https://lore.kernel.org/r/20250607200454.73587-7-ebiggers@kernel.org Signed-off-by: Eric Biggers <ebiggers@kernel.org>
162 lines
4 KiB
C
162 lines
4 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* crc32-mips.c - CRC32 and CRC32C using optional MIPSr6 instructions
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*
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* Module based on arm64/crypto/crc32-arm.c
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*
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* Copyright (C) 2014 Linaro Ltd <yazen.ghannam@linaro.org>
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* Copyright (C) 2018 MIPS Tech, LLC
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*/
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#include <linux/cpufeature.h>
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#include <asm/mipsregs.h>
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#include <linux/unaligned.h>
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#ifndef TOOLCHAIN_SUPPORTS_CRC
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#define _ASM_SET_CRC(OP, SZ, TYPE) \
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_ASM_MACRO_3R(OP, rt, rs, rt2, \
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".ifnc \\rt, \\rt2\n\t" \
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".error \"invalid operands \\\"" #OP " \\rt,\\rs,\\rt2\\\"\"\n\t" \
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".endif\n\t" \
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_ASM_INSN_IF_MIPS(0x7c00000f | (__rt << 16) | (__rs << 21) | \
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((SZ) << 6) | ((TYPE) << 8)) \
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_ASM_INSN32_IF_MM(0x00000030 | (__rs << 16) | (__rt << 21) | \
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((SZ) << 14) | ((TYPE) << 3)))
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#define _ASM_UNSET_CRC(op, SZ, TYPE) ".purgem " #op "\n\t"
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#else /* !TOOLCHAIN_SUPPORTS_CRC */
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#define _ASM_SET_CRC(op, SZ, TYPE) ".set\tcrc\n\t"
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#define _ASM_UNSET_CRC(op, SZ, TYPE)
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#endif
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#define __CRC32(crc, value, op, SZ, TYPE) \
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do { \
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__asm__ __volatile__( \
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".set push\n\t" \
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_ASM_SET_CRC(op, SZ, TYPE) \
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#op " %0, %1, %0\n\t" \
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_ASM_UNSET_CRC(op, SZ, TYPE) \
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".set pop" \
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: "+r" (crc) \
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: "r" (value)); \
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} while (0)
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#define _CRC32_crc32b(crc, value) __CRC32(crc, value, crc32b, 0, 0)
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#define _CRC32_crc32h(crc, value) __CRC32(crc, value, crc32h, 1, 0)
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#define _CRC32_crc32w(crc, value) __CRC32(crc, value, crc32w, 2, 0)
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#define _CRC32_crc32d(crc, value) __CRC32(crc, value, crc32d, 3, 0)
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#define _CRC32_crc32cb(crc, value) __CRC32(crc, value, crc32cb, 0, 1)
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#define _CRC32_crc32ch(crc, value) __CRC32(crc, value, crc32ch, 1, 1)
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#define _CRC32_crc32cw(crc, value) __CRC32(crc, value, crc32cw, 2, 1)
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#define _CRC32_crc32cd(crc, value) __CRC32(crc, value, crc32cd, 3, 1)
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#define _CRC32(crc, value, size, op) \
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_CRC32_##op##size(crc, value)
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#define CRC32(crc, value, size) \
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_CRC32(crc, value, size, crc32)
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#define CRC32C(crc, value, size) \
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_CRC32(crc, value, size, crc32c)
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static __ro_after_init DEFINE_STATIC_KEY_FALSE(have_crc32);
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static inline u32 crc32_le_arch(u32 crc, const u8 *p, size_t len)
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{
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if (!static_branch_likely(&have_crc32))
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return crc32_le_base(crc, p, len);
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if (IS_ENABLED(CONFIG_64BIT)) {
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for (; len >= sizeof(u64); p += sizeof(u64), len -= sizeof(u64)) {
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u64 value = get_unaligned_le64(p);
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CRC32(crc, value, d);
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}
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if (len & sizeof(u32)) {
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u32 value = get_unaligned_le32(p);
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CRC32(crc, value, w);
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p += sizeof(u32);
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}
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} else {
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for (; len >= sizeof(u32); len -= sizeof(u32)) {
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u32 value = get_unaligned_le32(p);
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CRC32(crc, value, w);
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p += sizeof(u32);
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}
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}
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if (len & sizeof(u16)) {
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u16 value = get_unaligned_le16(p);
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CRC32(crc, value, h);
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p += sizeof(u16);
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}
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if (len & sizeof(u8)) {
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u8 value = *p++;
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CRC32(crc, value, b);
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}
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return crc;
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}
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static inline u32 crc32c_arch(u32 crc, const u8 *p, size_t len)
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{
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if (!static_branch_likely(&have_crc32))
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return crc32c_base(crc, p, len);
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if (IS_ENABLED(CONFIG_64BIT)) {
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for (; len >= sizeof(u64); p += sizeof(u64), len -= sizeof(u64)) {
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u64 value = get_unaligned_le64(p);
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CRC32C(crc, value, d);
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}
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if (len & sizeof(u32)) {
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u32 value = get_unaligned_le32(p);
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CRC32C(crc, value, w);
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p += sizeof(u32);
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}
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} else {
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for (; len >= sizeof(u32); len -= sizeof(u32)) {
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u32 value = get_unaligned_le32(p);
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CRC32C(crc, value, w);
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p += sizeof(u32);
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}
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}
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if (len & sizeof(u16)) {
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u16 value = get_unaligned_le16(p);
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CRC32C(crc, value, h);
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p += sizeof(u16);
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}
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if (len & sizeof(u8)) {
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u8 value = *p++;
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CRC32C(crc, value, b);
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}
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return crc;
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}
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#define crc32_be_arch crc32_be_base /* not implemented on this arch */
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#define crc32_mod_init_arch crc32_mod_init_arch
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static inline void crc32_mod_init_arch(void)
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{
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if (cpu_have_feature(cpu_feature(MIPS_CRC32)))
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static_branch_enable(&have_crc32);
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}
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static inline u32 crc32_optimizations_arch(void)
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{
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if (static_key_enabled(&have_crc32))
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return CRC32_LE_OPTIMIZATION | CRC32C_OPTIMIZATION;
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return 0;
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}
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