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2705bce5b4
Reworked BCM_TCS_CMD macro in order to fix warnings from sparse: drivers/clk/qcom/clk-rpmh.c:270:28: warning: restricted __le32 degrades to integer drivers/clk/qcom/clk-rpmh.c:270:28: warning: restricted __le32 degrades to integer While at it, used u32_encode_bits which made the code easier to follow and removed unnecessary shift definitions. The use of cpu_to_le32 was wrong and thus removed. Signed-off-by: Eugen Hristev <eugen.hristev@linaro.org> Reviewed-by: Stephen Boyd <sboyd@kernel.org> Link: https://lore.kernel.org/r/20241129142446.407443-1-eugen.hristev@linaro.org Signed-off-by: Bjorn Andersson <andersson@kernel.org>
79 lines
2.5 KiB
C
79 lines
2.5 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2016-2019, The Linux Foundation. All rights reserved.
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*/
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#ifndef __SOC_QCOM_TCS_H__
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#define __SOC_QCOM_TCS_H__
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#include <linux/bitfield.h>
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#include <linux/bits.h>
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#define MAX_RPMH_PAYLOAD 16
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/**
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* rpmh_state: state for the request
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*
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* RPMH_SLEEP_STATE: State of the resource when the processor subsystem
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* is powered down. There is no client using the
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* resource actively.
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* RPMH_WAKE_ONLY_STATE: Resume resource state to the value previously
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* requested before the processor was powered down.
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* RPMH_ACTIVE_ONLY_STATE: Active or AMC mode requests. Resource state
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* is aggregated immediately.
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*/
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enum rpmh_state {
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RPMH_SLEEP_STATE,
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RPMH_WAKE_ONLY_STATE,
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RPMH_ACTIVE_ONLY_STATE,
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};
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/**
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* struct tcs_cmd: an individual request to RPMH.
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*
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* @addr: the address of the resource slv_id:18:16 | offset:0:15
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* @data: the resource state request
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* @wait: ensure that this command is complete before returning.
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* Setting "wait" here only makes sense during rpmh_write_batch() for
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* active-only transfers, this is because:
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* rpmh_write() - Always waits.
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* (DEFINE_RPMH_MSG_ONSTACK will set .wait_for_compl)
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* rpmh_write_async() - Never waits.
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* (There's no request completion callback)
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*/
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struct tcs_cmd {
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u32 addr;
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u32 data;
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u32 wait;
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};
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/**
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* struct tcs_request: A set of tcs_cmds sent together in a TCS
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*
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* @state: state for the request.
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* @wait_for_compl: wait until we get a response from the h/w accelerator
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* (same as setting cmd->wait for all commands in the request)
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* @num_cmds: the number of @cmds in this request
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* @cmds: an array of tcs_cmds
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*/
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struct tcs_request {
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enum rpmh_state state;
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u32 wait_for_compl;
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u32 num_cmds;
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struct tcs_cmd *cmds;
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};
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#define BCM_TCS_CMD_COMMIT_MASK BIT(30)
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#define BCM_TCS_CMD_VALID_MASK BIT(29)
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#define BCM_TCS_CMD_VOTE_MASK GENMASK(13, 0)
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#define BCM_TCS_CMD_VOTE_Y_MASK GENMASK(13, 0)
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#define BCM_TCS_CMD_VOTE_X_MASK GENMASK(27, 14)
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/* Construct a Bus Clock Manager (BCM) specific TCS command */
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#define BCM_TCS_CMD(commit, valid, vote_x, vote_y) \
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(u32_encode_bits(commit, BCM_TCS_CMD_COMMIT_MASK) | \
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u32_encode_bits(valid, BCM_TCS_CMD_VALID_MASK) | \
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u32_encode_bits(vote_x, BCM_TCS_CMD_VOTE_X_MASK) | \
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u32_encode_bits(vote_y, BCM_TCS_CMD_VOTE_Y_MASK))
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#endif /* __SOC_QCOM_TCS_H__ */
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