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52dbf84857
The Allwinner A523/T527 SoCs have four CCUs, this adds the binding for the main and the PRCM R-CCU. The source clock list differs in some annoying details, and folding this into the existing Allwinner CCU clock binding document gets quite unwieldy, so create a new document for these CCUs. Add the new compatible string, along with the required input clock lists. This conditionally describes the input clock lists, to make adding support for the other two CCUs easier. Also add the DT binding headers, listing all the clocks with their ID numbers. Signed-off-by: Andre Przywara <andre.przywara@arm.com> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Link: https://patch.msgid.link/20250307002628.10684-5-andre.przywara@arm.com Signed-off-by: Chen-Yu Tsai <wens@csie.org>
88 lines
2.2 KiB
C
88 lines
2.2 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
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/*
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* Copyright (c) 2024 Arm Ltd.
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*/
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#ifndef _DT_BINDINGS_RST_SUN55I_A523_CCU_H_
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#define _DT_BINDINGS_RST_SUN55I_A523_CCU_H_
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#define RST_MBUS 0
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#define RST_BUS_NSI 1
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#define RST_BUS_DE 2
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#define RST_BUS_DI 3
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#define RST_BUS_G2D 4
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#define RST_BUS_SYS 5
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#define RST_BUS_GPU 6
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#define RST_BUS_CE 7
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#define RST_BUS_SYS_CE 8
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#define RST_BUS_VE 9
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#define RST_BUS_DMA 10
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#define RST_BUS_MSGBOX 11
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#define RST_BUS_SPINLOCK 12
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#define RST_BUS_CPUXTIMER 13
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#define RST_BUS_DBG 14
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#define RST_BUS_PWM0 15
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#define RST_BUS_PWM1 16
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#define RST_BUS_DRAM 17
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#define RST_BUS_NAND 18
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#define RST_BUS_MMC0 19
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#define RST_BUS_MMC1 20
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#define RST_BUS_MMC2 21
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#define RST_BUS_SYSDAP 22
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#define RST_BUS_UART0 23
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#define RST_BUS_UART1 24
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#define RST_BUS_UART2 25
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#define RST_BUS_UART3 26
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#define RST_BUS_UART4 27
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#define RST_BUS_UART5 28
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#define RST_BUS_UART6 29
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#define RST_BUS_UART7 30
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#define RST_BUS_I2C0 31
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#define RST_BUS_I2C1 32
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#define RST_BUS_I2C2 33
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#define RST_BUS_I2C3 34
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#define RST_BUS_I2C4 35
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#define RST_BUS_I2C5 36
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#define RST_BUS_CAN 37
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#define RST_BUS_SPI0 38
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#define RST_BUS_SPI1 39
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#define RST_BUS_SPI2 40
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#define RST_BUS_SPIFC 41
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#define RST_BUS_EMAC0 42
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#define RST_BUS_EMAC1 43
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#define RST_BUS_IR_RX 44
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#define RST_BUS_IR_TX 45
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#define RST_BUS_GPADC0 46
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#define RST_BUS_GPADC1 47
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#define RST_BUS_THS 48
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#define RST_USB_PHY0 49
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#define RST_USB_PHY1 50
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#define RST_BUS_OHCI0 51
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#define RST_BUS_OHCI1 52
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#define RST_BUS_EHCI0 53
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#define RST_BUS_EHCI1 54
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#define RST_BUS_OTG 55
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#define RST_BUS_3 56
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#define RST_BUS_LRADC 57
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#define RST_BUS_PCIE_USB3 58
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#define RST_BUS_DISPLAY0_TOP 59
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#define RST_BUS_DISPLAY1_TOP 60
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#define RST_BUS_HDMI_MAIN 61
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#define RST_BUS_HDMI_SUB 62
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#define RST_BUS_MIPI_DSI0 63
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#define RST_BUS_MIPI_DSI1 64
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#define RST_BUS_TCON_LCD0 65
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#define RST_BUS_TCON_LCD1 66
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#define RST_BUS_TCON_LCD2 67
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#define RST_BUS_TCON_TV0 68
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#define RST_BUS_TCON_TV1 69
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#define RST_BUS_LVDS0 70
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#define RST_BUS_LVDS1 71
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#define RST_BUS_EDP 72
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#define RST_BUS_VIDEO_OUT0 73
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#define RST_BUS_VIDEO_OUT1 74
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#define RST_BUS_LEDC 75
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#define RST_BUS_CSI 76
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#define RST_BUS_ISP 77
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#endif /* _DT_BINDINGS_RST_SUN55I_A523_CCU_H_ */
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