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28300ecedc
Add NSSCC clock and reset definitions for ipq9574. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Devi Priya <quic_devipriy@quicinc.com> Signed-off-by: Manikanta Mylavarapu <quic_mmanikan@quicinc.com> Link: https://lore.kernel.org/r/20250313110359.242491-4-quic_mmanikan@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
134 lines
3.8 KiB
C
134 lines
3.8 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2023, 2025 The Linux Foundation. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_RESET_IPQ_NSSCC_9574_H
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#define _DT_BINDINGS_RESET_IPQ_NSSCC_9574_H
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#define EDMA_HW_RESET 0
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#define NSS_CC_CE_BCR 1
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#define NSS_CC_CLC_BCR 2
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#define NSS_CC_EIP197_BCR 3
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#define NSS_CC_HAQ_BCR 4
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#define NSS_CC_IMEM_BCR 5
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#define NSS_CC_MAC_BCR 6
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#define NSS_CC_PPE_BCR 7
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#define NSS_CC_UBI_BCR 8
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#define NSS_CC_UNIPHY_BCR 9
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#define UBI3_CLKRST_CLAMP_ENABLE 10
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#define UBI3_CORE_CLAMP_ENABLE 11
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#define UBI2_CLKRST_CLAMP_ENABLE 12
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#define UBI2_CORE_CLAMP_ENABLE 13
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#define UBI1_CLKRST_CLAMP_ENABLE 14
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#define UBI1_CORE_CLAMP_ENABLE 15
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#define UBI0_CLKRST_CLAMP_ENABLE 16
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#define UBI0_CORE_CLAMP_ENABLE 17
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#define NSSNOC_NSS_CSR_ARES 18
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#define NSS_CSR_ARES 19
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#define PPE_BTQ_ARES 20
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#define PPE_IPE_ARES 21
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#define PPE_ARES 22
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#define PPE_CFG_ARES 23
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#define PPE_EDMA_ARES 24
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#define PPE_EDMA_CFG_ARES 25
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#define CRY_PPE_ARES 26
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#define NSSNOC_PPE_ARES 27
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#define NSSNOC_PPE_CFG_ARES 28
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#define PORT1_MAC_ARES 29
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#define PORT2_MAC_ARES 30
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#define PORT3_MAC_ARES 31
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#define PORT4_MAC_ARES 32
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#define PORT5_MAC_ARES 33
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#define PORT6_MAC_ARES 34
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#define XGMAC0_PTP_REF_ARES 35
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#define XGMAC1_PTP_REF_ARES 36
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#define XGMAC2_PTP_REF_ARES 37
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#define XGMAC3_PTP_REF_ARES 38
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#define XGMAC4_PTP_REF_ARES 39
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#define XGMAC5_PTP_REF_ARES 40
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#define HAQ_AHB_ARES 41
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#define HAQ_AXI_ARES 42
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#define NSSNOC_HAQ_AHB_ARES 43
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#define NSSNOC_HAQ_AXI_ARES 44
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#define CE_APB_ARES 45
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#define CE_AXI_ARES 46
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#define NSSNOC_CE_APB_ARES 47
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#define NSSNOC_CE_AXI_ARES 48
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#define CRYPTO_ARES 49
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#define NSSNOC_CRYPTO_ARES 50
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#define NSSNOC_NC_AXI0_1_ARES 51
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#define UBI0_CORE_ARES 52
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#define UBI1_CORE_ARES 53
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#define UBI2_CORE_ARES 54
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#define UBI3_CORE_ARES 55
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#define NC_AXI0_ARES 56
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#define UTCM0_ARES 57
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#define NC_AXI1_ARES 58
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#define UTCM1_ARES 59
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#define NC_AXI2_ARES 60
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#define UTCM2_ARES 61
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#define NC_AXI3_ARES 62
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#define UTCM3_ARES 63
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#define NSSNOC_NC_AXI0_ARES 64
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#define AHB0_ARES 65
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#define INTR0_AHB_ARES 66
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#define AHB1_ARES 67
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#define INTR1_AHB_ARES 68
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#define AHB2_ARES 69
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#define INTR2_AHB_ARES 70
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#define AHB3_ARES 71
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#define INTR3_AHB_ARES 72
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#define NSSNOC_AHB0_ARES 73
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#define NSSNOC_INT0_AHB_ARES 74
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#define AXI0_ARES 75
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#define AXI1_ARES 76
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#define AXI2_ARES 77
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#define AXI3_ARES 78
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#define NSSNOC_AXI0_ARES 79
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#define IMEM_QSB_ARES 80
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#define NSSNOC_IMEM_QSB_ARES 81
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#define IMEM_AHB_ARES 82
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#define NSSNOC_IMEM_AHB_ARES 83
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#define UNIPHY_PORT1_RX_ARES 84
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#define UNIPHY_PORT1_TX_ARES 85
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#define UNIPHY_PORT2_RX_ARES 86
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#define UNIPHY_PORT2_TX_ARES 87
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#define UNIPHY_PORT3_RX_ARES 88
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#define UNIPHY_PORT3_TX_ARES 89
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#define UNIPHY_PORT4_RX_ARES 90
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#define UNIPHY_PORT4_TX_ARES 91
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#define UNIPHY_PORT5_RX_ARES 92
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#define UNIPHY_PORT5_TX_ARES 93
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#define UNIPHY_PORT6_RX_ARES 94
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#define UNIPHY_PORT6_TX_ARES 95
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#define PORT1_RX_ARES 96
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#define PORT1_TX_ARES 97
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#define PORT2_RX_ARES 98
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#define PORT2_TX_ARES 99
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#define PORT3_RX_ARES 100
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#define PORT3_TX_ARES 101
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#define PORT4_RX_ARES 102
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#define PORT4_TX_ARES 103
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#define PORT5_RX_ARES 104
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#define PORT5_TX_ARES 105
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#define PORT6_RX_ARES 106
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#define PORT6_TX_ARES 107
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#define PPE_FULL_RESET 108
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#define UNIPHY0_SOFT_RESET 109
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#define UNIPHY1_SOFT_RESET 110
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#define UNIPHY2_SOFT_RESET 111
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#define UNIPHY_PORT1_ARES 112
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#define UNIPHY_PORT2_ARES 113
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#define UNIPHY_PORT3_ARES 114
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#define UNIPHY_PORT4_ARES 115
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#define UNIPHY_PORT5_ARES 116
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#define UNIPHY_PORT6_ARES 117
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#define NSSPORT1_RESET 118
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#define NSSPORT2_RESET 119
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#define NSSPORT3_RESET 120
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#define NSSPORT4_RESET 121
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#define NSSPORT5_RESET 122
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#define NSSPORT6_RESET 123
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#endif
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