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The BPMP firmware on Tegra264 defines a set of IDs for clock and reset resources. These are not enumerations but provided by hardware, and 0 is a reserved value, hence the numbering starts at 1. Acked-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Thierry Reding <treding@nvidia.com>
92 lines
3.1 KiB
C
92 lines
3.1 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/* Copyright (c) 2022-2025, NVIDIA CORPORATION. All rights reserved. */
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#ifndef DT_BINDINGS_RESET_NVIDIA_TEGRA264_H
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#define DT_BINDINGS_RESET_NVIDIA_TEGRA264_H
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#define TEGRA264_RESET_APE_TKE 1
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#define TEGRA264_RESET_CEC 2
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#define TEGRA264_RESET_ADSP_ALL 3
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#define TEGRA264_RESET_RCE_ALL 4
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#define TEGRA264_RESET_UFSHC 5
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#define TEGRA264_RESET_UFSHC_AXI_M 6
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#define TEGRA264_RESET_UFSHC_LP_SEQ 7
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#define TEGRA264_RESET_DPAUX 8
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#define TEGRA264_RESET_EQOS_PCS 9
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#define TEGRA264_RESET_HWPM 10
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#define TEGRA264_RESET_I2C1 11
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#define TEGRA264_RESET_I2C2 12
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#define TEGRA264_RESET_I2C3 13
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#define TEGRA264_RESET_I2C4 14
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#define TEGRA264_RESET_I2C6 15
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#define TEGRA264_RESET_I2C7 16
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#define TEGRA264_RESET_I2C8 17
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#define TEGRA264_RESET_I2C9 18
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#define TEGRA264_RESET_ISP 19
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#define TEGRA264_RESET_LA 20
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#define TEGRA264_RESET_NVCSI 21
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#define TEGRA264_RESET_EQOS_MAC 22
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#define TEGRA264_RESET_PWM10 23
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#define TEGRA264_RESET_PWM2 24
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#define TEGRA264_RESET_PWM3 25
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#define TEGRA264_RESET_PWM4 26
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#define TEGRA264_RESET_PWM5 27
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#define TEGRA264_RESET_PWM9 28
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#define TEGRA264_RESET_QSPI0 29
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#define TEGRA264_RESET_HDA 30
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#define TEGRA264_RESET_HDACODEC 31
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#define TEGRA264_RESET_I2C0 32
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#define TEGRA264_RESET_I2C10 33
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#define TEGRA264_RESET_SDMMC1 34
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#define TEGRA264_RESET_MIPI_CAL 35
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#define TEGRA264_RESET_SPI1 36
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#define TEGRA264_RESET_SPI2 37
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#define TEGRA264_RESET_SPI3 38
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#define TEGRA264_RESET_SPI4 39
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#define TEGRA264_RESET_SPI5 40
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#define TEGRA264_RESET_SPI7 41
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#define TEGRA264_RESET_SPI8 42
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#define TEGRA264_RESET_SPI9 43
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#define TEGRA264_RESET_TACH0 44
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#define TEGRA264_RESET_TSEC 45
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#define TEGRA264_RESET_VI 46
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#define TEGRA264_RESET_VI1 47
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#define TEGRA264_RESET_PVA0_ALL 48
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#define TEGRA264_RESET_VIC 49
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#define TEGRA264_RESET_MPHY_CLK_CTL 50
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#define TEGRA264_RESET_MPHY_L0_RX 51
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#define TEGRA264_RESET_MPHY_L0_TX 52
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#define TEGRA264_RESET_MPHY_L1_RX 53
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#define TEGRA264_RESET_MPHY_L1_TX 54
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#define TEGRA264_RESET_ISP1 55
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#define TEGRA264_RESET_I2C11 56
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#define TEGRA264_RESET_I2C12 57
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#define TEGRA264_RESET_I2C14 58
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#define TEGRA264_RESET_I2C15 59
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#define TEGRA264_RESET_I2C16 60
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#define TEGRA264_RESET_EQOS_MACSEC 61
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#define TEGRA264_RESET_MGBE0_PCS 62
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#define TEGRA264_RESET_MGBE0_MAC 63
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#define TEGRA264_RESET_MGBE0_MACSEC 64
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#define TEGRA264_RESET_MGBE1_PCS 65
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#define TEGRA264_RESET_MGBE1_MAC 66
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#define TEGRA264_RESET_MGBE1_MACSEC 67
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#define TEGRA264_RESET_MGBE2_PCS 68
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#define TEGRA264_RESET_MGBE2_MAC 69
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#define TEGRA264_RESET_MGBE2_MACSEC 70
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#define TEGRA264_RESET_MGBE3_PCS 71
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#define TEGRA264_RESET_MGBE3_MAC 72
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#define TEGRA264_RESET_MGBE3_MACSEC 73
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#define TEGRA264_RESET_ADSP_CORE0 74
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#define TEGRA264_RESET_ADSP_CORE1 75
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#define TEGRA264_RESET_APE 76
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#define TEGRA264_RESET_XUSB1_PADCTL 77
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#define TEGRA264_RESET_AON_CPU_ALL 78
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#define TEGRA264_RESET_AON_HSP 79
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#define TEGRA264_RESET_UART4 80
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#define TEGRA264_RESET_UART5 81
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#define TEGRA264_RESET_UART9 82
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#define TEGRA264_RESET_UART10 83
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#define TEGRA264_RESET_UART8 84
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#endif /* DT_BINDINGS_RESET_NVIDIA_TEGRA264_H */
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