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91a7088096
Each data lane on a CSI-2 C-PHY bus uses three phase encoding and is constructed from three physical wires. The wires are referred to as A, B and C and their default order is ABC. However to ease hardware design the specification allows for the wires to be switched in any order. Add a vendor neutral property to describe the line order used. The property name 'line-orders', the possible values it can be assigned and there names are taken from the MIPI Discovery and Configuration (DisCo) Specification for Imaging. Signed-off-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se> Reviewed-by: Rob Herring (Arm) <robh@kernel.org> Signed-off-by: Sakari Ailus <sakari.ailus@linux.intel.com> Signed-off-by: Mauro Carvalho Chehab <mchehab+huawei@kernel.org>
23 lines
766 B
C
23 lines
766 B
C
/* SPDX-License-Identifier: (GPL-2.0-only OR MIT) */
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/*
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* Copyright (C) 2022 Laurent Pinchart <laurent.pinchart@ideasonboard.com>
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*/
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#ifndef __DT_BINDINGS_MEDIA_VIDEO_INTERFACES_H__
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#define __DT_BINDINGS_MEDIA_VIDEO_INTERFACES_H__
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#define MEDIA_BUS_TYPE_CSI2_CPHY 1
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#define MEDIA_BUS_TYPE_CSI1 2
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#define MEDIA_BUS_TYPE_CCP2 3
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#define MEDIA_BUS_TYPE_CSI2_DPHY 4
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#define MEDIA_BUS_TYPE_PARALLEL 5
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#define MEDIA_BUS_TYPE_BT656 6
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#define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_ABC 0
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#define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_ACB 1
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#define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_BAC 2
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#define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_BCA 3
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#define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_CAB 4
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#define MEDIA_BUS_CSI2_CPHY_LINE_ORDER_CBA 5
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#endif /* __DT_BINDINGS_MEDIA_VIDEO_INTERFACES_H__ */
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