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Document the RPMh Network-On-Chip Interconnect of the Milos (e.g. SM7635) SoC. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20250709-sm7635-icc-v3-1-c446203c3b3a@fairphone.com Signed-off-by: Georgi Djakov <djakov@kernel.org>
141 lines
3.7 KiB
C
141 lines
3.7 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2023-2024, Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com>
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*/
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#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_MILOS_H
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#define __DT_BINDINGS_INTERCONNECT_QCOM_MILOS_H
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#define MASTER_QUP_1 0
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#define MASTER_UFS_MEM 1
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#define MASTER_USB3_0 2
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#define SLAVE_A1NOC_SNOC 3
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#define MASTER_QDSS_BAM 0
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#define MASTER_QSPI_0 1
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#define MASTER_QUP_0 2
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#define MASTER_CRYPTO 3
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#define MASTER_IPA 4
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#define MASTER_QDSS_ETR 5
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#define MASTER_QDSS_ETR_1 6
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#define MASTER_SDCC_1 7
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#define MASTER_SDCC_2 8
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#define SLAVE_A2NOC_SNOC 9
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#define MASTER_QUP_CORE_0 0
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#define MASTER_QUP_CORE_1 1
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#define SLAVE_QUP_CORE_0 2
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#define SLAVE_QUP_CORE_1 3
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#define MASTER_CNOC_CFG 0
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#define SLAVE_AHB2PHY_SOUTH 1
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#define SLAVE_AHB2PHY_NORTH 2
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#define SLAVE_CAMERA_CFG 3
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#define SLAVE_CLK_CTL 4
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#define SLAVE_RBCPR_CX_CFG 5
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#define SLAVE_RBCPR_MXA_CFG 6
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#define SLAVE_CRYPTO_0_CFG 7
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#define SLAVE_CX_RDPM 8
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#define SLAVE_GFX3D_CFG 9
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#define SLAVE_IMEM_CFG 10
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#define SLAVE_CNOC_MSS 11
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#define SLAVE_MX_2_RDPM 12
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#define SLAVE_MX_RDPM 13
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#define SLAVE_PDM 14
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#define SLAVE_QDSS_CFG 15
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#define SLAVE_QSPI_0 16
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#define SLAVE_QUP_0 17
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#define SLAVE_QUP_1 18
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#define SLAVE_SDC1 19
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#define SLAVE_SDCC_2 20
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#define SLAVE_TCSR 21
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#define SLAVE_TLMM 22
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#define SLAVE_UFS_MEM_CFG 23
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#define SLAVE_USB3_0 24
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#define SLAVE_VENUS_CFG 25
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#define SLAVE_VSENSE_CTRL_CFG 26
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#define SLAVE_WLAN 27
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#define SLAVE_CNOC_MNOC_HF_CFG 28
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#define SLAVE_CNOC_MNOC_SF_CFG 29
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#define SLAVE_NSP_QTB_CFG 30
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#define SLAVE_PCIE_ANOC_CFG 31
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#define SLAVE_WLAN_Q6_THROTTLE_CFG 32
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#define SLAVE_SERVICE_CNOC_CFG 33
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#define SLAVE_QDSS_STM 34
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#define SLAVE_TCU 35
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#define MASTER_GEM_NOC_CNOC 0
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#define MASTER_GEM_NOC_PCIE_SNOC 1
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#define SLAVE_AOSS 2
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#define SLAVE_DISPLAY_CFG 3
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#define SLAVE_IPA_CFG 4
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#define SLAVE_IPC_ROUTER_CFG 5
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#define SLAVE_PCIE_0_CFG 6
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#define SLAVE_PCIE_1_CFG 7
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#define SLAVE_PRNG 8
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#define SLAVE_TME_CFG 9
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#define SLAVE_APPSS 10
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#define SLAVE_CNOC_CFG 11
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#define SLAVE_DDRSS_CFG 12
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#define SLAVE_IMEM 13
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#define SLAVE_PIMEM 14
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#define SLAVE_SERVICE_CNOC 15
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#define SLAVE_PCIE_0 16
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#define SLAVE_PCIE_1 17
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#define MASTER_GPU_TCU 0
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#define MASTER_SYS_TCU 1
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#define MASTER_APPSS_PROC 2
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#define MASTER_GFX3D 3
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#define MASTER_LPASS_GEM_NOC 4
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#define MASTER_MSS_PROC 5
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#define MASTER_MNOC_HF_MEM_NOC 6
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#define MASTER_MNOC_SF_MEM_NOC 7
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#define MASTER_COMPUTE_NOC 8
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#define MASTER_ANOC_PCIE_GEM_NOC 9
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#define MASTER_SNOC_GC_MEM_NOC 10
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#define MASTER_SNOC_SF_MEM_NOC 11
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#define MASTER_WLAN_Q6 12
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#define SLAVE_GEM_NOC_CNOC 13
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#define SLAVE_LLCC 14
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#define SLAVE_MEM_NOC_PCIE_SNOC 15
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#define MASTER_LPASS_PROC 0
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#define SLAVE_LPASS_GEM_NOC 1
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#define MASTER_LLCC 0
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#define SLAVE_EBI1 1
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#define MASTER_CAMNOC_HF 0
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#define MASTER_CAMNOC_ICP 1
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#define MASTER_CAMNOC_SF 2
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#define MASTER_MDP 3
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#define MASTER_VIDEO 4
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#define MASTER_CNOC_MNOC_HF_CFG 5
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#define MASTER_CNOC_MNOC_SF_CFG 6
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#define SLAVE_MNOC_HF_MEM_NOC 7
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#define SLAVE_MNOC_SF_MEM_NOC 8
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#define SLAVE_SERVICE_MNOC_HF 9
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#define SLAVE_SERVICE_MNOC_SF 10
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#define MASTER_CDSP_PROC 0
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#define SLAVE_CDSP_MEM_NOC 1
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#define MASTER_PCIE_ANOC_CFG 0
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#define MASTER_PCIE_0 1
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#define MASTER_PCIE_1 2
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#define SLAVE_ANOC_PCIE_GEM_NOC 3
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#define SLAVE_SERVICE_PCIE_ANOC 4
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#define MASTER_A1NOC_SNOC 0
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#define MASTER_A2NOC_SNOC 1
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#define MASTER_APSS_NOC 2
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#define MASTER_CNOC_SNOC 3
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#define MASTER_PIMEM 4
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#define MASTER_GIC 5
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#define SLAVE_SNOC_GEM_NOC_GC 6
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#define SLAVE_SNOC_GEM_NOC_SF 7
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#endif
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