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2a76193f7c
Add the SDHI high-speed clock (SDHI_CLKHS) definition for the Renesas RZ/T2H (R9A09G077) and RZ/N2H (R9A09G087) SoCs. SDHI_CLKHS is used as a core clock for the SDHI IP and operates at 800MHz. Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> Link: https://lore.kernel.org/20250625141705.151383-2-prabhakar.mahadev-lad.rj@bp.renesas.com Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
29 lines
885 B
C
29 lines
885 B
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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*
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* Copyright (C) 2025 Renesas Electronics Corp.
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*/
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#ifndef __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__
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#define __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__
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#include <dt-bindings/clock/renesas-cpg-mssr.h>
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/* R9A09G087 CPG Core Clocks */
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#define R9A09G087_CLK_CA55C0 0
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#define R9A09G087_CLK_CA55C1 1
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#define R9A09G087_CLK_CA55C2 2
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#define R9A09G087_CLK_CA55C3 3
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#define R9A09G087_CLK_CA55S 4
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#define R9A09G087_CLK_CR52_CPU0 5
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#define R9A09G087_CLK_CR52_CPU1 6
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#define R9A09G087_CLK_CKIO 7
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#define R9A09G087_CLK_PCLKAH 8
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#define R9A09G087_CLK_PCLKAM 9
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#define R9A09G087_CLK_PCLKAL 10
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#define R9A09G087_CLK_PCLKGPTL 11
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#define R9A09G087_CLK_PCLKH 12
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#define R9A09G087_CLK_PCLKM 13
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#define R9A09G087_CLK_PCLKL 14
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#define R9A09G087_SDHI_CLKHS 15
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#endif /* __DT_BINDINGS_CLOCK_RENESAS_R9A09G087_CPG_H__ */
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