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b5975ce461
Add device tree bindings for the camera clock controller on Qualcomm SC8180X platform. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Satya Priya Kakitapalli <quic_skakitap@quicinc.com> Link: https://lore.kernel.org/r/20250512-sc8180x-camcc-support-v4-2-8fb1d3265f52@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
181 lines
6 KiB
C
181 lines
6 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2025, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_CAM_CC_SC8180X_H
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#define _DT_BINDINGS_CLK_QCOM_CAM_CC_SC8180X_H
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/* CAM_CC clocks */
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#define CAM_CC_BPS_AHB_CLK 0
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#define CAM_CC_BPS_AREG_CLK 1
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#define CAM_CC_BPS_AXI_CLK 2
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#define CAM_CC_BPS_CLK 3
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#define CAM_CC_BPS_CLK_SRC 4
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#define CAM_CC_CAMNOC_AXI_CLK 5
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#define CAM_CC_CAMNOC_AXI_CLK_SRC 6
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#define CAM_CC_CAMNOC_DCD_XO_CLK 7
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#define CAM_CC_CCI_0_CLK 8
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#define CAM_CC_CCI_0_CLK_SRC 9
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#define CAM_CC_CCI_1_CLK 10
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#define CAM_CC_CCI_1_CLK_SRC 11
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#define CAM_CC_CCI_2_CLK 12
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#define CAM_CC_CCI_2_CLK_SRC 13
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#define CAM_CC_CCI_3_CLK 14
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#define CAM_CC_CCI_3_CLK_SRC 15
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#define CAM_CC_CORE_AHB_CLK 16
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#define CAM_CC_CPAS_AHB_CLK 17
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#define CAM_CC_CPHY_RX_CLK_SRC 18
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#define CAM_CC_CSI0PHYTIMER_CLK 19
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#define CAM_CC_CSI0PHYTIMER_CLK_SRC 20
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#define CAM_CC_CSI1PHYTIMER_CLK 21
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#define CAM_CC_CSI1PHYTIMER_CLK_SRC 22
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#define CAM_CC_CSI2PHYTIMER_CLK 23
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#define CAM_CC_CSI2PHYTIMER_CLK_SRC 24
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#define CAM_CC_CSI3PHYTIMER_CLK 25
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#define CAM_CC_CSI3PHYTIMER_CLK_SRC 26
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#define CAM_CC_CSIPHY0_CLK 27
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#define CAM_CC_CSIPHY1_CLK 28
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#define CAM_CC_CSIPHY2_CLK 29
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#define CAM_CC_CSIPHY3_CLK 30
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#define CAM_CC_FAST_AHB_CLK_SRC 31
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#define CAM_CC_FD_CORE_CLK 32
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#define CAM_CC_FD_CORE_CLK_SRC 33
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#define CAM_CC_FD_CORE_UAR_CLK 34
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#define CAM_CC_ICP_AHB_CLK 35
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#define CAM_CC_ICP_CLK 36
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#define CAM_CC_ICP_CLK_SRC 37
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#define CAM_CC_IFE_0_AXI_CLK 38
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#define CAM_CC_IFE_0_CLK 39
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#define CAM_CC_IFE_0_CLK_SRC 40
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#define CAM_CC_IFE_0_CPHY_RX_CLK 41
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#define CAM_CC_IFE_0_CSID_CLK 42
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#define CAM_CC_IFE_0_CSID_CLK_SRC 43
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#define CAM_CC_IFE_0_DSP_CLK 44
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#define CAM_CC_IFE_1_AXI_CLK 45
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#define CAM_CC_IFE_1_CLK 46
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#define CAM_CC_IFE_1_CLK_SRC 47
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#define CAM_CC_IFE_1_CPHY_RX_CLK 48
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#define CAM_CC_IFE_1_CSID_CLK 49
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#define CAM_CC_IFE_1_CSID_CLK_SRC 50
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#define CAM_CC_IFE_1_DSP_CLK 51
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#define CAM_CC_IFE_2_AXI_CLK 52
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#define CAM_CC_IFE_2_CLK 53
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#define CAM_CC_IFE_2_CLK_SRC 54
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#define CAM_CC_IFE_2_CPHY_RX_CLK 55
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#define CAM_CC_IFE_2_CSID_CLK 56
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#define CAM_CC_IFE_2_CSID_CLK_SRC 57
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#define CAM_CC_IFE_2_DSP_CLK 58
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#define CAM_CC_IFE_3_AXI_CLK 59
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#define CAM_CC_IFE_3_CLK 60
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#define CAM_CC_IFE_3_CLK_SRC 61
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#define CAM_CC_IFE_3_CPHY_RX_CLK 62
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#define CAM_CC_IFE_3_CSID_CLK 63
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#define CAM_CC_IFE_3_CSID_CLK_SRC 64
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#define CAM_CC_IFE_3_DSP_CLK 65
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#define CAM_CC_IFE_LITE_0_CLK 66
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#define CAM_CC_IFE_LITE_0_CLK_SRC 67
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#define CAM_CC_IFE_LITE_0_CPHY_RX_CLK 68
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#define CAM_CC_IFE_LITE_0_CSID_CLK 69
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#define CAM_CC_IFE_LITE_0_CSID_CLK_SRC 70
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#define CAM_CC_IFE_LITE_1_CLK 71
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#define CAM_CC_IFE_LITE_1_CLK_SRC 72
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#define CAM_CC_IFE_LITE_1_CPHY_RX_CLK 73
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#define CAM_CC_IFE_LITE_1_CSID_CLK 74
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#define CAM_CC_IFE_LITE_1_CSID_CLK_SRC 75
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#define CAM_CC_IFE_LITE_2_CLK 76
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#define CAM_CC_IFE_LITE_2_CLK_SRC 77
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#define CAM_CC_IFE_LITE_2_CPHY_RX_CLK 78
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#define CAM_CC_IFE_LITE_2_CSID_CLK 79
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#define CAM_CC_IFE_LITE_2_CSID_CLK_SRC 80
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#define CAM_CC_IFE_LITE_3_CLK 81
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#define CAM_CC_IFE_LITE_3_CLK_SRC 82
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#define CAM_CC_IFE_LITE_3_CPHY_RX_CLK 83
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#define CAM_CC_IFE_LITE_3_CSID_CLK 84
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#define CAM_CC_IFE_LITE_3_CSID_CLK_SRC 85
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#define CAM_CC_IPE_0_AHB_CLK 86
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#define CAM_CC_IPE_0_AREG_CLK 87
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#define CAM_CC_IPE_0_AXI_CLK 88
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#define CAM_CC_IPE_0_CLK 89
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#define CAM_CC_IPE_0_CLK_SRC 90
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#define CAM_CC_IPE_1_AHB_CLK 91
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#define CAM_CC_IPE_1_AREG_CLK 92
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#define CAM_CC_IPE_1_AXI_CLK 93
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#define CAM_CC_IPE_1_CLK 94
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#define CAM_CC_JPEG_CLK 95
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#define CAM_CC_JPEG_CLK_SRC 96
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#define CAM_CC_LRME_CLK 97
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#define CAM_CC_LRME_CLK_SRC 98
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#define CAM_CC_MCLK0_CLK 99
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#define CAM_CC_MCLK0_CLK_SRC 100
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#define CAM_CC_MCLK1_CLK 101
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#define CAM_CC_MCLK1_CLK_SRC 102
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#define CAM_CC_MCLK2_CLK 103
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#define CAM_CC_MCLK2_CLK_SRC 104
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#define CAM_CC_MCLK3_CLK 105
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#define CAM_CC_MCLK3_CLK_SRC 106
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#define CAM_CC_MCLK4_CLK 107
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#define CAM_CC_MCLK4_CLK_SRC 108
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#define CAM_CC_MCLK5_CLK 109
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#define CAM_CC_MCLK5_CLK_SRC 110
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#define CAM_CC_MCLK6_CLK 111
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#define CAM_CC_MCLK6_CLK_SRC 112
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#define CAM_CC_MCLK7_CLK 113
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#define CAM_CC_MCLK7_CLK_SRC 114
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#define CAM_CC_PLL0 115
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#define CAM_CC_PLL0_OUT_EVEN 116
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#define CAM_CC_PLL0_OUT_ODD 117
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#define CAM_CC_PLL1 118
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#define CAM_CC_PLL2 119
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#define CAM_CC_PLL2_OUT_MAIN 120
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#define CAM_CC_PLL3 121
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#define CAM_CC_PLL4 122
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#define CAM_CC_PLL5 123
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#define CAM_CC_PLL6 124
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#define CAM_CC_SLOW_AHB_CLK_SRC 125
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#define CAM_CC_XO_CLK_SRC 126
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/* CAM_CC power domains */
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#define BPS_GDSC 0
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#define IFE_0_GDSC 1
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#define IFE_1_GDSC 2
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#define IFE_2_GDSC 3
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#define IFE_3_GDSC 4
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#define IPE_0_GDSC 5
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#define IPE_1_GDSC 6
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#define TITAN_TOP_GDSC 7
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/* CAM_CC resets */
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#define CAM_CC_BPS_BCR 0
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#define CAM_CC_CAMNOC_BCR 1
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#define CAM_CC_CCI_BCR 2
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#define CAM_CC_CPAS_BCR 3
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#define CAM_CC_CSI0PHY_BCR 4
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#define CAM_CC_CSI1PHY_BCR 5
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#define CAM_CC_CSI2PHY_BCR 6
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#define CAM_CC_CSI3PHY_BCR 7
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#define CAM_CC_FD_BCR 8
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#define CAM_CC_ICP_BCR 9
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#define CAM_CC_IFE_0_BCR 10
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#define CAM_CC_IFE_1_BCR 11
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#define CAM_CC_IFE_2_BCR 12
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#define CAM_CC_IFE_3_BCR 13
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#define CAM_CC_IFE_LITE_0_BCR 14
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#define CAM_CC_IFE_LITE_1_BCR 15
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#define CAM_CC_IFE_LITE_2_BCR 16
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#define CAM_CC_IFE_LITE_3_BCR 17
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#define CAM_CC_IPE_0_BCR 18
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#define CAM_CC_IPE_1_BCR 19
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#define CAM_CC_JPEG_BCR 20
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#define CAM_CC_LRME_BCR 21
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#define CAM_CC_MCLK0_BCR 22
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#define CAM_CC_MCLK1_BCR 23
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#define CAM_CC_MCLK2_BCR 24
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#define CAM_CC_MCLK3_BCR 25
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#define CAM_CC_MCLK4_BCR 26
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#define CAM_CC_MCLK5_BCR 27
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#define CAM_CC_MCLK6_BCR 28
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#define CAM_CC_MCLK7_BCR 29
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#endif
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