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7867cb6575
Add device tree bindings for the video clock controller on Qualcomm SA8775P platform. Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20241011-sa8775p-mm-v4-resend-patches-v5-1-4a9f17dc683a@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
47 lines
1.4 KiB
C
47 lines
1.4 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_SA8775P_VIDEO_CC_H
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#define _DT_BINDINGS_CLK_QCOM_SA8775P_VIDEO_CC_H
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/* VIDEO_CC clocks */
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#define VIDEO_CC_AHB_CLK 0
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#define VIDEO_CC_AHB_CLK_SRC 1
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#define VIDEO_CC_MVS0_CLK 2
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#define VIDEO_CC_MVS0_CLK_SRC 3
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#define VIDEO_CC_MVS0_DIV_CLK_SRC 4
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#define VIDEO_CC_MVS0C_CLK 5
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#define VIDEO_CC_MVS0C_DIV2_DIV_CLK_SRC 6
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#define VIDEO_CC_MVS1_CLK 7
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#define VIDEO_CC_MVS1_CLK_SRC 8
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#define VIDEO_CC_MVS1_DIV_CLK_SRC 9
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#define VIDEO_CC_MVS1C_CLK 10
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#define VIDEO_CC_MVS1C_DIV2_DIV_CLK_SRC 11
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#define VIDEO_CC_PLL_LOCK_MONITOR_CLK 12
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#define VIDEO_CC_SLEEP_CLK 13
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#define VIDEO_CC_SLEEP_CLK_SRC 14
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#define VIDEO_CC_SM_DIV_CLK_SRC 15
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#define VIDEO_CC_SM_OBS_CLK 16
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#define VIDEO_CC_XO_CLK 17
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#define VIDEO_CC_XO_CLK_SRC 18
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#define VIDEO_PLL0 19
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#define VIDEO_PLL1 20
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/* VIDEO_CC power domains */
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#define VIDEO_CC_MVS0C_GDSC 0
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#define VIDEO_CC_MVS0_GDSC 1
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#define VIDEO_CC_MVS1C_GDSC 2
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#define VIDEO_CC_MVS1_GDSC 3
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/* VIDEO_CC resets */
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#define VIDEO_CC_INTERFACE_BCR 0
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#define VIDEO_CC_MVS0_BCR 1
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#define VIDEO_CC_MVS0C_CLK_ARES 2
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#define VIDEO_CC_MVS0C_BCR 3
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#define VIDEO_CC_MVS1_BCR 4
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#define VIDEO_CC_MVS1C_CLK_ARES 5
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#define VIDEO_CC_MVS1C_BCR 6
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#endif
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