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3590dfbdd1
Add DT bindings for the Graphics clock on QCS615 platforms. Add the relevant DT include definitions as well. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Taniya Das <quic_tdas@quicinc.com> Link: https://lore.kernel.org/r/20250702-qcs615-mm-v10-clock-controllers-v11-6-9c216e1615ab@quicinc.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
39 lines
1.1 KiB
C
39 lines
1.1 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2024, Qualcomm Innovation Center, Inc. All rights reserved.
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_GPU_CC_QCS615_H
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#define _DT_BINDINGS_CLK_QCOM_GPU_CC_QCS615_H
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/* GPU_CC clocks */
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#define CRC_DIV_PLL0 0
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#define CRC_DIV_PLL1 1
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#define GPU_CC_PLL0 2
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#define GPU_CC_PLL1 3
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#define GPU_CC_CRC_AHB_CLK 4
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#define GPU_CC_CX_GFX3D_CLK 5
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#define GPU_CC_CX_GFX3D_SLV_CLK 6
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#define GPU_CC_CX_GMU_CLK 7
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#define GPU_CC_CX_SNOC_DVM_CLK 8
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#define GPU_CC_CXO_AON_CLK 9
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#define GPU_CC_CXO_CLK 10
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#define GPU_CC_GMU_CLK_SRC 11
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#define GPU_CC_GX_GFX3D_CLK 12
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#define GPU_CC_GX_GFX3D_CLK_SRC 13
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#define GPU_CC_GX_GMU_CLK 14
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#define GPU_CC_HLOS1_VOTE_GPU_SMMU_CLK 15
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#define GPU_CC_SLEEP_CLK 16
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/* GPU_CC power domains */
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#define CX_GDSC 0
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#define GX_GDSC 1
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/* GPU_CC resets */
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#define GPU_CC_CX_BCR 0
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#define GPU_CC_GFX3D_AON_BCR 1
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#define GPU_CC_GMU_BCR 2
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#define GPU_CC_GX_BCR 3
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#define GPU_CC_XO_BCR 4
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#endif
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