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63edb206a3
Add bindings documentation for the Milos (e.g. SM7635) Display Clock Controller. Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Signed-off-by: Luca Weiss <luca.weiss@fairphone.com> Link: https://lore.kernel.org/r/20250715-sm7635-clocks-v3-6-18f9faac4984@fairphone.com Signed-off-by: Bjorn Andersson <andersson@kernel.org>
61 lines
2.1 KiB
C
61 lines
2.1 KiB
C
/* SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) */
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/*
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* Copyright (c) 2023, Qualcomm Innovation Center, Inc. All rights reserved.
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* Copyright (c) 2025, Luca Weiss <luca.weiss@fairphone.com>
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*/
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#ifndef _DT_BINDINGS_CLK_QCOM_DISP_CC_MILOS_H
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#define _DT_BINDINGS_CLK_QCOM_DISP_CC_MILOS_H
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/* DISP_CC clocks */
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#define DISP_CC_PLL0 0
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#define DISP_CC_MDSS_ACCU_CLK 1
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#define DISP_CC_MDSS_AHB1_CLK 2
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#define DISP_CC_MDSS_AHB_CLK 3
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#define DISP_CC_MDSS_AHB_CLK_SRC 4
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#define DISP_CC_MDSS_BYTE0_CLK 5
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#define DISP_CC_MDSS_BYTE0_CLK_SRC 6
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#define DISP_CC_MDSS_BYTE0_DIV_CLK_SRC 7
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#define DISP_CC_MDSS_BYTE0_INTF_CLK 8
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#define DISP_CC_MDSS_DPTX0_AUX_CLK 9
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#define DISP_CC_MDSS_DPTX0_AUX_CLK_SRC 10
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#define DISP_CC_MDSS_DPTX0_CRYPTO_CLK 11
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#define DISP_CC_MDSS_DPTX0_LINK_CLK 12
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#define DISP_CC_MDSS_DPTX0_LINK_CLK_SRC 13
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#define DISP_CC_MDSS_DPTX0_LINK_DIV_CLK_SRC 14
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#define DISP_CC_MDSS_DPTX0_LINK_INTF_CLK 15
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#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK 16
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#define DISP_CC_MDSS_DPTX0_PIXEL0_CLK_SRC 17
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#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK 18
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#define DISP_CC_MDSS_DPTX0_PIXEL1_CLK_SRC 19
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#define DISP_CC_MDSS_DPTX0_USB_ROUTER_LINK_INTF_CLK 20
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#define DISP_CC_MDSS_ESC0_CLK 21
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#define DISP_CC_MDSS_ESC0_CLK_SRC 22
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#define DISP_CC_MDSS_MDP1_CLK 23
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#define DISP_CC_MDSS_MDP_CLK 24
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#define DISP_CC_MDSS_MDP_CLK_SRC 25
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#define DISP_CC_MDSS_MDP_LUT1_CLK 26
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#define DISP_CC_MDSS_MDP_LUT_CLK 27
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#define DISP_CC_MDSS_NON_GDSC_AHB_CLK 28
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#define DISP_CC_MDSS_PCLK0_CLK 29
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#define DISP_CC_MDSS_PCLK0_CLK_SRC 30
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#define DISP_CC_MDSS_RSCC_AHB_CLK 31
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#define DISP_CC_MDSS_RSCC_VSYNC_CLK 32
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#define DISP_CC_MDSS_VSYNC1_CLK 33
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#define DISP_CC_MDSS_VSYNC_CLK 34
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#define DISP_CC_MDSS_VSYNC_CLK_SRC 35
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#define DISP_CC_SLEEP_CLK 36
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#define DISP_CC_SLEEP_CLK_SRC 37
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#define DISP_CC_XO_CLK 38
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#define DISP_CC_XO_CLK_SRC 39
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/* DISP_CC resets */
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#define DISP_CC_MDSS_CORE_BCR 0
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#define DISP_CC_MDSS_CORE_INT2_BCR 1
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#define DISP_CC_MDSS_RSCC_BCR 2
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/* DISP_CC power domains */
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#define DISP_CC_MDSS_CORE_GDSC 0
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#define DISP_CC_MDSS_CORE_INT2_GDSC 1
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#endif
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