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b4f62001cc
Add RMII clock selection for ENETC0 and ENETC1. Signed-off-by: Wei Fang <wei.fang@nxp.com> Acked-by: Rob Herring (Arm) <robh@kernel.org> Link: https://lore.kernel.org/r/20240829011849.364987-3-wei.fang@nxp.com Signed-off-by: Abel Vesa <abel.vesa@linaro.org>
31 lines
861 B
C
31 lines
861 B
C
/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
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/*
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* Copyright 2024 NXP
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*/
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#ifndef __DT_BINDINGS_CLOCK_IMX95_H
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#define __DT_BINDINGS_CLOCK_IMX95_H
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#define IMX95_CLK_VPUBLK_WAVE 0
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#define IMX95_CLK_VPUBLK_JPEG_ENC 1
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#define IMX95_CLK_VPUBLK_JPEG_DEC 2
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#define IMX95_CLK_CAMBLK_CSI2_FOR0 0
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#define IMX95_CLK_CAMBLK_CSI2_FOR1 1
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#define IMX95_CLK_CAMBLK_ISP_AXI 2
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#define IMX95_CLK_CAMBLK_ISP_PIXEL 3
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#define IMX95_CLK_CAMBLK_ISP 4
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#define IMX95_CLK_DISPMIX_LVDS_PHY_DIV 0
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#define IMX95_CLK_DISPMIX_LVDS_CH0_GATE 1
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#define IMX95_CLK_DISPMIX_LVDS_CH1_GATE 2
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#define IMX95_CLK_DISPMIX_PIX_DI0_GATE 3
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#define IMX95_CLK_DISPMIX_PIX_DI1_GATE 4
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#define IMX95_CLK_DISPMIX_ENG0_SEL 0
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#define IMX95_CLK_DISPMIX_ENG1_SEL 1
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#define IMX95_CLK_NETCMIX_ENETC0_RMII 0
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#define IMX95_CLK_NETCMIX_ENETC1_RMII 1
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#endif /* __DT_BINDINGS_CLOCK_IMX95_H */
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