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1c9eb9e684
Add the `microchip,sama7d65-pmc` compatible string to the existing binding, since the SAMA7D65 PMC shares the same properties and clock requirements as the SAMA7G5. Export MCK3 and MCK5 to be accessed and referenced in DT to assign to the clocks property for sama7d65 SoC. Signed-off-by: Dharma Balasubiramani <dharma.b@microchip.com> Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com> Reviewed-by: Claudiu Beznea <claudiu.beznea@tuxon.dev> Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org> Link: https://lore.kernel.org/r/5252a28531deaee67af1edd8e72d45ca57783464.1733505542.git.Ryan.Wanner@microchip.com [claudiu.beznea: use tabs instead of spaces in include/dt-bindings/clock/at91.h] Signed-off-by: Claudiu Beznea <claudiu.beznea@tuxon.dev>
66 lines
1.7 KiB
C
66 lines
1.7 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* This header provides constants for AT91 pmc status.
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*
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* The constants defined in this header are being used in dts.
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*/
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#ifndef _DT_BINDINGS_CLK_AT91_H
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#define _DT_BINDINGS_CLK_AT91_H
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#define PMC_TYPE_CORE 0
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#define PMC_TYPE_SYSTEM 1
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#define PMC_TYPE_PERIPHERAL 2
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#define PMC_TYPE_GCK 3
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#define PMC_TYPE_PROGRAMMABLE 4
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#define PMC_SLOW 0
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#define PMC_MCK 1
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#define PMC_UTMI 2
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#define PMC_MAIN 3
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#define PMC_MCK2 4
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#define PMC_I2S0_MUX 5
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#define PMC_I2S1_MUX 6
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#define PMC_PLLACK 7
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#define PMC_PLLBCK 8
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#define PMC_AUDIOPLLCK 9
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#define PMC_AUDIOPINCK 10
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/* SAMA7G5 */
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#define PMC_CPUPLL (PMC_MAIN + 1)
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#define PMC_SYSPLL (PMC_MAIN + 2)
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#define PMC_DDRPLL (PMC_MAIN + 3)
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#define PMC_IMGPLL (PMC_MAIN + 4)
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#define PMC_BAUDPLL (PMC_MAIN + 5)
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#define PMC_AUDIOPMCPLL (PMC_MAIN + 6)
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#define PMC_AUDIOIOPLL (PMC_MAIN + 7)
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#define PMC_ETHPLL (PMC_MAIN + 8)
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#define PMC_CPU (PMC_MAIN + 9)
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#define PMC_MCK1 (PMC_MAIN + 10)
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/* SAM9X7 */
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#define PMC_PLLADIV2 (PMC_MAIN + 11)
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#define PMC_LVDSPLL (PMC_MAIN + 12)
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/* SAMA7D65 */
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#define PMC_MCK3 (PMC_MAIN + 13)
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#define PMC_MCK5 (PMC_MAIN + 14)
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#ifndef AT91_PMC_MOSCS
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#define AT91_PMC_MOSCS 0 /* MOSCS Flag */
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#define AT91_PMC_LOCKA 1 /* PLLA Lock */
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#define AT91_PMC_LOCKB 2 /* PLLB Lock */
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#define AT91_PMC_MCKRDY 3 /* Master Clock */
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#define AT91_PMC_LOCKU 6 /* UPLL Lock */
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#define AT91_PMC_PCKRDY(id) (8 + (id)) /* Programmable Clock */
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#define AT91_PMC_MOSCSELS 16 /* Main Oscillator Selection */
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#define AT91_PMC_MOSCRCS 17 /* Main On-Chip RC */
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#define AT91_PMC_CFDEV 18 /* Clock Failure Detector Event */
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#define AT91_PMC_GCKRDY 24 /* Generated Clocks */
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#endif
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/* Slow clock. */
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#define SCKC_MD_SLCK 0
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#define SCKC_TD_SLCK 1
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#endif
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